【摘要】：隨著集成電路的不斷發(fā)展,越來越多的混合信號電路和模擬集成電路采用數(shù)字輔助單元來完成電路的設(shè)計,如在模數(shù)轉(zhuǎn)換器中采用數(shù)字校準(zhǔn)模塊,更有些將電路的大部分功能數(shù)字化,如全數(shù)字鎖相環(huán)。數(shù)字集成電路對時間域的信號具有良好的處理能力,時間數(shù)字轉(zhuǎn)換器(TDC)作為模擬連續(xù)時間信號與數(shù)字離散信號之間的橋梁,也開始被用來構(gòu)建一些模擬集成電路。此外,在高能物理和粒子物理領(lǐng)域中,TDC是高精度時間間隔測量系統(tǒng)的核心單元。因此,TDC的研究對于集成電路設(shè)計和高精度測量都有重要意義。本論文主要研究高速高精度時間數(shù)字轉(zhuǎn)換器,基于TSMC 0.18μm CMOS工藝,采用全定制和半定制相結(jié)合的方法,完成電路的設(shè)計與實現(xiàn)。為了實現(xiàn)低于門延時的精度,在比較各種高精度TDC結(jié)構(gòu)以及它們的優(yōu)缺點之后,選擇以游標(biāo)型TDC為原型,整個電路由三部分構(gòu)成：雙通道游標(biāo)延時線電路以及讀出電路和編碼電路。其中,游標(biāo)延時線電路采用全定制方法設(shè)計,主要實現(xiàn)延時單元延時值的精確控制；讀出電路和編碼電路采用半定制方法設(shè)計,前者主要完成溫度計碼的暫存和對齊,后者則采用流水線結(jié)構(gòu)以保證500MHz的轉(zhuǎn)換速度。這種數(shù)模混合設(shè)計方法在保證電路性能的同時,也降低了電路的設(shè)計難度。為了方便芯片測試,在芯片中還設(shè)計了內(nèi)嵌激勵信號模塊,該模塊通過全定制方法設(shè)計,能夠產(chǎn)生若干組均勻分布在整個動態(tài)范圍之中的時間間隔。所設(shè)計的TDC芯片已完成了后仿真、流片和測試,整體版圖面積為1.25×0.675mm2。測試結(jié)果表明,該TDC芯片能夠滿足設(shè)計指標(biāo),在500MHz方波信號和1.8V電源電壓下總的電流為66.2mA�；跍y試結(jié)果,論文還進一步研究分析了提高游標(biāo)型TDC性能的方法,并采用減小單級延時線長度的方法設(shè)計了基于層次結(jié)構(gòu)的高性能TDC,該TDC由第一級延時單元和第二級高精度TDC構(gòu)成,其中高精度TDC包含四路16級游標(biāo)延遲線電路。該TDC整體版圖面積為0.735×0.92mm2,后仿真結(jié)果表明,高性能TDC性能達到指標(biāo)要求,且面積和功耗有一定程度的改進。
[Abstract]:With the continuous development of integrated circuits, more and more mixed signal circuits and analog integrated circuits use digital auxiliary units to complete the circuit design, such as the use of digital calibration modules in analog-to-digital converters. Some digitize most of the functions of the circuit, such as all-digital phase-locked loops. Digital integrated circuit (DIC) has good processing ability for time domain signal. As a bridge between analog continuous time signal and digital discrete signal, time digital converter (TDC) has been used to construct some analog integrated circuits. In addition, in the field of high energy physics and particle physics, TDC is the core unit of high precision time interval measurement system. Therefore, the research of TDC is very important for IC design and high precision measurement. In this paper, the high speed and high precision time digital converter is studied. Based on TSMC 0.18 渭 m CMOS technology, the circuit is designed and implemented by the combination of full customization and semi-customization. In order to achieve the accuracy lower than the gate delay, after comparing various high-precision TDC structures and their advantages and disadvantages, the Vernier TDC is chosen as the prototype. The whole circuit consists of three parts: double channel Vernier delay line circuit, readout circuit and coding circuit. Among them, the Vernier delay line circuit is designed by full-custom method, which mainly realizes the accurate control of delay value of delay unit, and the readout circuit and coding circuit are designed by semi-custom method, the former mainly completes the transient storage and alignment of thermometer code, The latter adopts pipeline structure to ensure the conversion speed of 500MHz. This method not only ensures the circuit performance, but also reduces the difficulty of circuit design. In order to facilitate the chip test, the embedded excitation signal module is designed in the chip. The module can produce several groups of time interval evenly distributed in the whole dynamic range by the method of full customization. The designed TDC chip has completed post-simulation, streaming and testing, and the overall layout area is 1.25 脳 0.675mm-2. The test results show that the TDC chip can meet the design requirements and the total current is 66.2 Ma under the 500MHz square wave signal and 1.8 V power supply voltage. Based on the test results, the methods to improve the performance of Vernier TDC are further studied and analyzed. The high performance TDC based on hierarchical structure is designed by reducing the length of single stage delay line. The TDC is composed of the first stage delay unit and the second stage high precision TDC. The high precision TDC contains four 16-stage Vernier delay line circuits. The overall layout area of the TDC is 0.735 脳 0.92mm2.After the simulation results show that the performance of the high performance TDC meets the requirements, and the area and power consumption are improved to a certain extent.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN402

【相似文獻】

相關(guān)期刊論文 前10條

1 ;12位數(shù)字轉(zhuǎn)換器插卡優(yōu)化多通道性能[J];電子設(shè)計技術(shù);2003年09期

2 ;美國國家半導(dǎo)體推出一系列共36款的全新模擬/數(shù)字轉(zhuǎn)換器[J];電子與電腦;2005年05期

3 ;拯救生命及保護嬰兒——模擬/數(shù)字轉(zhuǎn)換器的神奇妙用[J];電子與電腦;2007年03期

4 李萃先;;模擬-數(shù)字轉(zhuǎn)換器的幾種新線路[J];電子計算機動態(tài);1963年01期

5 Robert S.Prill;模擬-數(shù)字轉(zhuǎn)換器[J];電子計算機參考資料;1970年05期

6 戎瑞;;微微秒時間分辨率的數(shù)字轉(zhuǎn)換器[J];激光與紅外;1979年08期

7 ;用數(shù)字/數(shù)字轉(zhuǎn)換器提高音頻性能[J];電子設(shè)計技術(shù);2001年04期

8 毛靜文,王照鋼,陳誠,任俊彥;模擬/數(shù)字轉(zhuǎn)換器的動態(tài)性能參數(shù)處理[J];微電子學(xué);2004年03期

9 舒立鵬;鄧利娟;陳建;;一種軸角數(shù)字轉(zhuǎn)換器的接口設(shè)計[J];工業(yè)控制計算機;2006年05期

10 ;阻抗數(shù)字轉(zhuǎn)換器解決復(fù)數(shù)測量的難題[J];電子設(shè)計技術(shù);2006年06期

相關(guān)會議論文 前1條

1 王君竹;范學(xué)磊;田勇;殷飛;;一種軟件旋變數(shù)字轉(zhuǎn)換器的設(shè)計與開發(fā)[A];自主創(chuàng)新、學(xué)術(shù)交流——第十屆河南省汽車工程科學(xué)技術(shù)研討會論文集[C];2013年

相關(guān)重要報紙文章 前1條

1 廣西 趙嘉云;1-VVire熱電偶數(shù)字轉(zhuǎn)換器MAX31850/MAX31851[N];電子報;2013年

相關(guān)碩士學(xué)位論文 前10條

1 邵琦;FPGA開關(guān)參數(shù)測試方法研究與實現(xiàn)[D];復(fù)旦大學(xué);2014年

2 李乾鋒;基于0.18um CMOS工藝的時間數(shù)字轉(zhuǎn)換器的設(shè)計與實現(xiàn)[D];東南大學(xué);2015年

3 佟寶麗;一種新型偽流水線時間—數(shù)字轉(zhuǎn)換器系統(tǒng)建模與關(guān)鍵技術(shù)的研究[D];復(fù)旦大學(xué);2010年

4 張根苗;內(nèi)插型時間數(shù)字轉(zhuǎn)換器設(shè)計[D];湖南大學(xué);2013年

5 宗士新;高分辨率數(shù)字時間轉(zhuǎn)換器的設(shè)計[D];哈爾濱工業(yè)大學(xué);2012年

6 豆衛(wèi)敏;基于全數(shù)字鎖相環(huán)的時間數(shù)字轉(zhuǎn)換器的研究[D];浙江工業(yè)大學(xué);2009年

7 李玉忠;高速時間—數(shù)字轉(zhuǎn)換器設(shè)計與實現(xiàn)[D];國防科學(xué)技術(shù)大學(xué);2008年

8 徐貴富;應(yīng)用集成電容數(shù)字轉(zhuǎn)換器的ECT系統(tǒng)設(shè)計及算法研究[D];北京交通大學(xué);2012年

9 田中一;游標(biāo)型時間數(shù)字轉(zhuǎn)換器的研究與設(shè)計[D];哈爾濱工業(yè)大學(xué);2012年

10 王曉露;基于單片機的旋轉(zhuǎn)變壓器—數(shù)字轉(zhuǎn)換器的研究[D];西北工業(yè)大學(xué);2006年

，

本文編號：2190234