【摘要】：隨著集成電路的不斷發(fā)展,越來越多的混合信號(hào)電路和模擬集成電路采用數(shù)字輔助單元來完成電路的設(shè)計(jì),如在模數(shù)轉(zhuǎn)換器中采用數(shù)字校準(zhǔn)模塊,更有些將電路的大部分功能數(shù)字化,如全數(shù)字鎖相環(huán)。數(shù)字集成電路對(duì)時(shí)間域的信號(hào)具有良好的處理能力,時(shí)間數(shù)字轉(zhuǎn)換器(TDC)作為模擬連續(xù)時(shí)間信號(hào)與數(shù)字離散信號(hào)之間的橋梁,也開始被用來構(gòu)建一些模擬集成電路。此外,在高能物理和粒子物理領(lǐng)域中,TDC是高精度時(shí)間間隔測(cè)量系統(tǒng)的核心單元。因此,TDC的研究對(duì)于集成電路設(shè)計(jì)和高精度測(cè)量都有重要意義。本論文主要研究高速高精度時(shí)間數(shù)字轉(zhuǎn)換器,基于TSMC 0.18μm CMOS工藝,采用全定制和半定制相結(jié)合的方法,完成電路的設(shè)計(jì)與實(shí)現(xiàn)。為了實(shí)現(xiàn)低于門延時(shí)的精度,在比較各種高精度TDC結(jié)構(gòu)以及它們的優(yōu)缺點(diǎn)之后,選擇以游標(biāo)型TDC為原型,整個(gè)電路由三部分構(gòu)成：雙通道游標(biāo)延時(shí)線電路以及讀出電路和編碼電路。其中,游標(biāo)延時(shí)線電路采用全定制方法設(shè)計(jì),主要實(shí)現(xiàn)延時(shí)單元延時(shí)值的精確控制；讀出電路和編碼電路采用半定制方法設(shè)計(jì),前者主要完成溫度計(jì)碼的暫存和對(duì)齊,后者則采用流水線結(jié)構(gòu)以保證500MHz的轉(zhuǎn)換速度。這種數(shù)�；旌显O(shè)計(jì)方法在保證電路性能的同時(shí),也降低了電路的設(shè)計(jì)難度。為了方便芯片測(cè)試,在芯片中還設(shè)計(jì)了內(nèi)嵌激勵(lì)信號(hào)模塊,該模塊通過全定制方法設(shè)計(jì),能夠產(chǎn)生若干組均勻分布在整個(gè)動(dòng)態(tài)范圍之中的時(shí)間間隔。所設(shè)計(jì)的TDC芯片已完成了后仿真、流片和測(cè)試,整體版圖面積為1.25×0.675mm2。測(cè)試結(jié)果表明,該TDC芯片能夠滿足設(shè)計(jì)指標(biāo),在500MHz方波信號(hào)和1.8V電源電壓下總的電流為66.2mA�；跍y(cè)試結(jié)果,論文還進(jìn)一步研究分析了提高游標(biāo)型TDC性能的方法,并采用減小單級(jí)延時(shí)線長(zhǎng)度的方法設(shè)計(jì)了基于層次結(jié)構(gòu)的高性能TDC,該TDC由第一級(jí)延時(shí)單元和第二級(jí)高精度TDC構(gòu)成,其中高精度TDC包含四路16級(jí)游標(biāo)延遲線電路。該TDC整體版圖面積為0.735×0.92mm2,后仿真結(jié)果表明,高性能TDC性能達(dá)到指標(biāo)要求,且面積和功耗有一定程度的改進(jìn)。
[Abstract]:With the continuous development of integrated circuits, more and more mixed signal circuits and analog integrated circuits use digital auxiliary units to complete the circuit design, such as the use of digital calibration modules in analog-to-digital converters. Some digitize most of the functions of the circuit, such as all-digital phase-locked loops. Digital integrated circuit (DIC) has good processing ability for time domain signal. As a bridge between analog continuous time signal and digital discrete signal, time digital converter (TDC) has been used to construct some analog integrated circuits. In addition, in the field of high energy physics and particle physics, TDC is the core unit of high precision time interval measurement system. Therefore, the research of TDC is very important for IC design and high precision measurement. In this paper, the high speed and high precision time digital converter is studied. Based on TSMC 0.18 渭 m CMOS technology, the circuit is designed and implemented by the combination of full customization and semi-customization. In order to achieve the accuracy lower than the gate delay, after comparing various high-precision TDC structures and their advantages and disadvantages, the Vernier TDC is chosen as the prototype. The whole circuit consists of three parts: double channel Vernier delay line circuit, readout circuit and coding circuit. Among them, the Vernier delay line circuit is designed by full-custom method, which mainly realizes the accurate control of delay value of delay unit, and the readout circuit and coding circuit are designed by semi-custom method, the former mainly completes the transient storage and alignment of thermometer code, The latter adopts pipeline structure to ensure the conversion speed of 500MHz. This method not only ensures the circuit performance, but also reduces the difficulty of circuit design. In order to facilitate the chip test, the embedded excitation signal module is designed in the chip. The module can produce several groups of time interval evenly distributed in the whole dynamic range by the method of full customization. The designed TDC chip has completed post-simulation, streaming and testing, and the overall layout area is 1.25 脳 0.675mm-2. The test results show that the TDC chip can meet the design requirements and the total current is 66.2 Ma under the 500MHz square wave signal and 1.8 V power supply voltage. Based on the test results, the methods to improve the performance of Vernier TDC are further studied and analyzed. The high performance TDC based on hierarchical structure is designed by reducing the length of single stage delay line. The TDC is composed of the first stage delay unit and the second stage high precision TDC. The high precision TDC contains four 16-stage Vernier delay line circuits. The overall layout area of the TDC is 0.735 脳 0.92mm2.After the simulation results show that the performance of the high performance TDC meets the requirements, and the area and power consumption are improved to a certain extent.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN402

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