新型碳基場效應(yīng)管在邏輯電路中的應(yīng)用研究
發(fā)布時間：2018-08-18 17:12
【摘要】：本文主要進(jìn)行基于溝道工程技術(shù)和柵工程技術(shù)碳基場效應(yīng)管器件以及由此構(gòu)成邏輯電路的分析和研究。在器件層次,利用非平衡格林函數(shù)(NEGF)和泊松方程(Poisson)自洽求解的量子力學(xué)模型,探討了溝道工程技術(shù)和柵工程技術(shù)對新型碳基場效應(yīng)管的輸運(yùn)特性的影響。在電路層次,基于查找表模型,利用SPICE仿真對新型碳基器件所構(gòu)建邏輯電路進(jìn)行性能分析和研究。通過本課題的研究,能夠為將來碳基器件和電路設(shè)計提供理論依據(jù)。本文的主要內(nèi)容有:首先,研究了基于石墨烯納米條帶材料的異質(zhì)柵氧化層結(jié)構(gòu)隧穿型場效應(yīng)管(GNR HTFET)并與其他相關(guān)結(jié)構(gòu)進(jìn)行比較分析。研究結(jié)果表明:這種新型結(jié)構(gòu)能夠降低關(guān)態(tài)電流,從而提高了開關(guān)電流比,并且亞閾值擺幅也有所減小。HTFET相對于普通結(jié)構(gòu)器件遲滯時間減小,電壓增益增大。其次,研究了基于碳納米管材料的源漏輕摻雜結(jié)構(gòu)隧穿型場效應(yīng)管(CNT LDDS-HTFET)的電學(xué)特性,并與其他相關(guān)結(jié)構(gòu)進(jìn)行比較分析。研究結(jié)果表明:這種新型結(jié)構(gòu)也能夠降低關(guān)態(tài)電流,從而提高了開關(guān)電流比。LDDS-HTFET相對于其他結(jié)構(gòu)器件截止頻率變大、柵電容減小,從而抑制了短溝道效應(yīng),使得LDDS-HTFET具有較好的高頻特性。最后,本文利用Verilog-A在所研究器件的轉(zhuǎn)移特性的基礎(chǔ)上建立查找表(LUT)模型,并在SPICE中構(gòu)建相應(yīng)的電路,分析其數(shù)字特性并與其他器件構(gòu)建的電路進(jìn)行比較。對于GNR HTFET所構(gòu)建的反相器,分析了其瞬態(tài)特性,并且與高K隧穿型場效應(yīng)管進(jìn)行了比較。研究結(jié)果表明:由GNR HTFET所構(gòu)建的反向器具有更小的功耗延遲積(PDP),且其PDP隨著柵長和供電電壓的變化率相對較小,也就是說GNR HTFET構(gòu)建的電路具有更好的穩(wěn)定性。然后,用LDDS-HTFET構(gòu)建了多種邏輯電路,驗證了這些邏輯電路的邏輯功能的正確性,并將其電路性能與普通結(jié)構(gòu)進(jìn)行比較分析,研究結(jié)果表明:該新型結(jié)構(gòu)所構(gòu)建的邏輯電路具有更低的延遲、功耗和PDP,并且所構(gòu)建的存儲器擁有相對較高的噪聲容限。
[Abstract]:In this paper, based on channel engineering technology and gate engineering technology, the analysis and research of carbon based FET devices and their logic circuits are carried out. At the device level, the influence of channel engineering technology and gate engineering technology on the transport characteristics of new carbon-based FET is discussed by using the quantum mechanical model of nonequilibrium Green function (NEGF) and Poisson equation (Poisson) self-consistent solution. At the circuit level, based on the lookup table model, the performance of the logic circuit constructed by the new carbon-based device is analyzed and studied by SPICE simulation. The research can provide theoretical basis for the design of carbon-based devices and circuits in the future. The main contents of this paper are as follows: firstly, the tunneling FET (GNR HTFET) based on graphene nanostrip is studied and compared with other related structures. The results show that the new structure can reduce the on-off current and increase the switching current ratio, and the sub-threshold swing is also reduced. The hysteresis time of the HTFET is reduced compared with that of the common structure device, and the voltage gain is increased. Secondly, the electrical properties of tunneling field effect transistor (CNT LDDS-HTFET) with light-doped source and drain structure based on carbon nanotube materials are studied and compared with other related structures. The results show that the new structure can also reduce the on-off current, thus increasing the switching current ratio. LDDS-HTFET increases the cutoff frequency compared with other devices, and the gate capacitance decreases, thus the short channel effect is restrained. The LDDS-HTFET has better high frequency characteristic. Finally, Verilog-A is used to build the lookup table (LUT) model on the basis of the transfer characteristics of the devices studied. The corresponding circuits are constructed in SPICE, and the digital characteristics are analyzed and compared with the circuits constructed by other devices. The transient characteristics of the inverter constructed by GNR HTFET are analyzed and compared with the high K tunneling FET. The results show that the inverter constructed by GNR HTFET has smaller power delay product (PDP),) and its PDP change rate with gate length and supply voltage is relatively small, which means that the circuit constructed by GNR HTFET has better stability. Then, a variety of logic circuits are constructed with LDDS-HTFET to verify the correctness of the logic functions of these logic circuits, and the performance of the circuits is compared with the common structure. The results show that the new structure has lower delay, lower power consumption and PDP, and the memory has a relatively high noise tolerance.
【學(xué)位授予單位】：南京郵電大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN386
本文編號：2190135
[Abstract]:In this paper, based on channel engineering technology and gate engineering technology, the analysis and research of carbon based FET devices and their logic circuits are carried out. At the device level, the influence of channel engineering technology and gate engineering technology on the transport characteristics of new carbon-based FET is discussed by using the quantum mechanical model of nonequilibrium Green function (NEGF) and Poisson equation (Poisson) self-consistent solution. At the circuit level, based on the lookup table model, the performance of the logic circuit constructed by the new carbon-based device is analyzed and studied by SPICE simulation. The research can provide theoretical basis for the design of carbon-based devices and circuits in the future. The main contents of this paper are as follows: firstly, the tunneling FET (GNR HTFET) based on graphene nanostrip is studied and compared with other related structures. The results show that the new structure can reduce the on-off current and increase the switching current ratio, and the sub-threshold swing is also reduced. The hysteresis time of the HTFET is reduced compared with that of the common structure device, and the voltage gain is increased. Secondly, the electrical properties of tunneling field effect transistor (CNT LDDS-HTFET) with light-doped source and drain structure based on carbon nanotube materials are studied and compared with other related structures. The results show that the new structure can also reduce the on-off current, thus increasing the switching current ratio. LDDS-HTFET increases the cutoff frequency compared with other devices, and the gate capacitance decreases, thus the short channel effect is restrained. The LDDS-HTFET has better high frequency characteristic. Finally, Verilog-A is used to build the lookup table (LUT) model on the basis of the transfer characteristics of the devices studied. The corresponding circuits are constructed in SPICE, and the digital characteristics are analyzed and compared with the circuits constructed by other devices. The transient characteristics of the inverter constructed by GNR HTFET are analyzed and compared with the high K tunneling FET. The results show that the inverter constructed by GNR HTFET has smaller power delay product (PDP),) and its PDP change rate with gate length and supply voltage is relatively small, which means that the circuit constructed by GNR HTFET has better stability. Then, a variety of logic circuits are constructed with LDDS-HTFET to verify the correctness of the logic functions of these logic circuits, and the performance of the circuits is compared with the common structure. The results show that the new structure has lower delay, lower power consumption and PDP, and the memory has a relatively high noise tolerance.
【學(xué)位授予單位】：南京郵電大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN386
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