10位低功耗SAR結(jié)構(gòu)ADC的研究與設計
發(fā)布時間：2018-08-17 16:49
【摘要】：模數(shù)轉(zhuǎn)換器(Analog to Digital Converters,ADC)是連接模擬信號和數(shù)字信號的橋梁。隨著數(shù)字信號處理技術(shù)的快速發(fā)展,模數(shù)轉(zhuǎn)換器得到非常廣泛的應用。逐次逼近型模數(shù)轉(zhuǎn)換器(Successive Approximation Register,SAR)由于其芯片面積小,轉(zhuǎn)換精度高,且能夠達到較高的采樣速率等優(yōu)點,近些年來已逐漸成為各大高校、研究所、以及企業(yè)的研究熱點。通常,逐次逼近模數(shù)轉(zhuǎn)換器(SAR ADC)廣泛應用于低功耗、低速(低于10MS/s)鄰域。近年來,隨著CMOS器件的特征尺寸的不斷縮小,器件速度的提高,5至10位SAR ADC的采樣率達到幾十MS/s到幾個GS/s。SAR ADC的特點是低功耗和低成本,在一些便攜式設備或低功率領(lǐng)域具有更強的吸引力。本文展現(xiàn)10位40MS/s的逐次逼近模數(shù)轉(zhuǎn)換器(SAR ADC)的研究與設計。提出了一種新的異步控制結(jié)構(gòu)。為了降低功耗,使用單調(diào)型電容開關(guān)算法。為了提高ADC的線性度,使用兩相不交疊時鐘。為了提高比較速度,比較器中加入多余的MOS晶體管。在0.18μm 1P6M CMOS工藝下,采用1.8V的電源,輸入頻率16.6525MHZ下的動態(tài)性能,40MS/s的SAR ADC的功耗僅為0.776mW,版圖面積0.77736mm~2,對應的信號失真比SNDR為59.9dB,無雜散動態(tài)范圍SFDR為68.5dB。
[Abstract]:Analog-to-digital converter (Analog to Digital converter) is a bridge between analog signal and digital signal. With the rapid development of digital signal processing technology, A-D converter is widely used. Because of its small chip area, high conversion precision and high sampling rate, successive approximation analog-to-digital converter (Successive Approximation) has become a research hotspot in universities, research institutes and enterprises in recent years. In general, successive approximation analog-to-digital converter (SAR ADC) is widely used in low power consumption, low speed (lower than 10MS/s) neighborhood. In recent years, with the continuous reduction of the characteristic size of CMOS devices, the improvement of device speed, the sampling rate of 5 to 10 bits SAR ADC can reach tens of MS/s to several GS/s.SAR ADC, which is characterized by low power consumption and low cost. More attractive in some portable devices or low power areas. This paper presents the research and design of a 10 bit 40MS/s successive approximation A / D converter (SAR ADC). A new asynchronous control structure is proposed. In order to reduce power consumption, the monotonic capacitor switch algorithm is used. In order to improve the linearity of ADC, two-phase non-overlapping clock is used. In order to improve the speed of comparison, extra MOS transistors are added to the comparator. Under 0.18 渭 m 1P6M CMOS process, the dynamic performance of 40 Ms / s SAR ADC with input frequency 16.6525MHZ is only 0.776 MW, the layout area is 0.77736 mm / 2, the corresponding signal distortion ratio is 59.9 dB, and the SFDR is 68.5 dB with a 1.8 V power supply.
【學位授予單位】：南京郵電大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN792
本文編號：2188286
[Abstract]:Analog-to-digital converter (Analog to Digital converter) is a bridge between analog signal and digital signal. With the rapid development of digital signal processing technology, A-D converter is widely used. Because of its small chip area, high conversion precision and high sampling rate, successive approximation analog-to-digital converter (Successive Approximation) has become a research hotspot in universities, research institutes and enterprises in recent years. In general, successive approximation analog-to-digital converter (SAR ADC) is widely used in low power consumption, low speed (lower than 10MS/s) neighborhood. In recent years, with the continuous reduction of the characteristic size of CMOS devices, the improvement of device speed, the sampling rate of 5 to 10 bits SAR ADC can reach tens of MS/s to several GS/s.SAR ADC, which is characterized by low power consumption and low cost. More attractive in some portable devices or low power areas. This paper presents the research and design of a 10 bit 40MS/s successive approximation A / D converter (SAR ADC). A new asynchronous control structure is proposed. In order to reduce power consumption, the monotonic capacitor switch algorithm is used. In order to improve the linearity of ADC, two-phase non-overlapping clock is used. In order to improve the speed of comparison, extra MOS transistors are added to the comparator. Under 0.18 渭 m 1P6M CMOS process, the dynamic performance of 40 Ms / s SAR ADC with input frequency 16.6525MHZ is only 0.776 MW, the layout area is 0.77736 mm / 2, the corresponding signal distortion ratio is 59.9 dB, and the SFDR is 68.5 dB with a 1.8 V power supply.
【學位授予單位】：南京郵電大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN792
【參考文獻】
相關(guān)期刊論文 前2條
1 袁小龍;趙夢戀;吳曉波;嚴曉浪;;低功耗高精度逐次逼近型模數(shù)轉(zhuǎn)換器的設計[J];浙江大學學報(工學版);2006年12期
2 殷勤;戚韜;吳光林;吳建輝;;多通道逐次逼近型10bit 40Ms/s模數(shù)轉(zhuǎn)換器的設計[J];電子器件;2006年04期
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