【摘要】：針對傳統(tǒng)反應(yīng)擴(kuò)散(reaction-diffusion,R-D)機(jī)制不適合納米互補(bǔ)金屬氧化物半導(dǎo)體(complementary metal oxide semiconductor,CMOS)集成電路正偏置溫度不穩(wěn)定性(positive bias temperature instability,PBTI)老化效應(yīng)分析的問題,文章采用電荷俘獲-釋放(trapping-detrapping,T-D)機(jī)制,結(jié)合線性分析和數(shù)據(jù)擬合方法,建立了N型金屬氧化物半導(dǎo)體(negative channel metal oxide semiconductor,NMOS)管PBTI效應(yīng)引起的基本邏輯門單元的時延退化預(yù)測模型。仿真實驗結(jié)果表明,采用該模型的電路PBTI老化預(yù)測結(jié)果與HSpice軟件仿真得到的時延預(yù)測結(jié)果相比,平均誤差為2%;關(guān)鍵路徑時序余量評估實驗表明,與基于R-D機(jī)制的老化時延模型相比,在相同的電路生命周期要求下,該模型需要的時序余量更小。
[Abstract]:Aiming at the problem that the traditional reaction-diffusion (R-D) mechanism is not suitable for the analysis of the aging effect of (complementary metal oxide semiconductor semiconductors in nanoscale complementary metal oxide semiconductors, the trapping-release mechanism is used in this paper. Based on linear analysis and data fitting method, a prediction model of delay degradation of basic logic gate cells caused by the PBTI effect of N-type metal oxide semiconductor (negative channel metal oxide semiconductors is established. The simulation results show that compared with the results of HSpice software, the average error of the PBTI aging prediction results of the circuit using this model is 2, and the critical path time series allowance evaluation experiment shows that, Compared with the aging delay model based on R-D mechanism, the model requires less time series margin under the same circuit life cycle requirements.
【作者單位】： 江蘇商貿(mào)職業(yè)學(xué)院藝術(shù)與電子信息學(xué)院;合肥工業(yè)大學(xué)電子科學(xué)與應(yīng)用物理學(xué)院;
【基金】：國家自然科學(xué)基金資助項目(61371025;61274036;61300212;61306049) 南通市應(yīng)用基礎(chǔ)研究科技計劃資助項目(GY12015037)
【分類號】：TN407
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本文編號：2184390