【摘要】：高壓互連(HVI)是功率集成電路(PIC)中的重要技術(shù),隨著PIC在結(jié)構(gòu)功能上的發(fā)展和應(yīng)用范圍上的增大,人們對(duì)功率集成電路中的高壓互連技術(shù)的要求也與日俱增。本文圍繞高壓互連技術(shù)進(jìn)行研究,重點(diǎn)研究高壓互連技術(shù)和Divided RESURF結(jié)構(gòu)。主要研究?jī)?nèi)容如下:1、通過(guò)建立模型研究了高壓互連線對(duì)器件的影響,并總結(jié)了包括厚絕緣層技術(shù)、降場(chǎng)層技術(shù)、場(chǎng)板技術(shù)。厚絕緣層技術(shù)增加了HVI與硅表面之間的距離;降場(chǎng)層技術(shù)引入了額外的經(jīng)過(guò)優(yōu)化的摻雜區(qū)域來(lái)輔助HVI下方的漂移區(qū)的耗盡。場(chǎng)板技術(shù)通過(guò)多種多樣的場(chǎng)板結(jié)構(gòu)來(lái)屏蔽HVI的影響。自屏蔽技術(shù)讓HVI避免跨過(guò)高壓結(jié)終端,從而不再需要額外的隔離結(jié)構(gòu)。2、通過(guò)仿真探究互連線對(duì)RESURF器件的影響因素,并根據(jù)仿真結(jié)果設(shè)計(jì)了包括:一種窄線寬的高壓互連結(jié)構(gòu)、一種部分場(chǎng)板屏蔽的高壓互連結(jié)構(gòu)、一種多片式高壓互連結(jié)構(gòu)等新型高壓互連結(jié)構(gòu)。3、使用Divided RESURF技術(shù)設(shè)計(jì)一種橫向雙擴(kuò)散金屬氧化物半導(dǎo)體場(chǎng)效應(yīng)晶體管(LDMOS),通過(guò)進(jìn)行二維工藝仿真,優(yōu)化其結(jié)構(gòu)和摻雜濃度等參數(shù),器件的擊穿耐壓達(dá)到818V,可用于600V的電平位移電路中。
[Abstract]:High voltage interconnection (HVI) is an important technology in power integrated circuit (PIC). With the development and application of PIC in structure and function, the demand for high voltage interconnection in power integrated circuit is increasing. This paper focuses on high-voltage interconnection technology and Divided RESURF structure. The main research contents are as follows: 1. The influence of high voltage interconnection on the device is studied by establishing a model, and including thick insulating layer technology, falling field layer technology and field board technology. Thick insulating layer technology increases the distance between HVI and silicon surface, and down-field layer technique introduces additional optimized doping regions to assist the depletion of drift regions beneath HVI. Field plate technology shields the influence of HVI through a variety of field plate structures. Self-shielding technology allows HVI to avoid crossing the high-voltage junction terminal, thus eliminating the need for additional isolation structure .2. the influence factors of interconnection on RESURF devices are explored through simulation. According to the simulation results, a high-voltage interconnection structure with narrow linewidth is designed. A high voltage interconnection structure with partial field board shielding, A new type of high voltage interconnection structure such as multichip high voltage interconnection. Using Divided RESURF technology, a transverse double diffusion metal oxide semiconductor field effect transistor (LDMOS),) is designed and its structure and doping concentration are optimized by two dimensional process simulation. The breakdown voltage of the device is 818 V, which can be used in 600 V level displacement circuit.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN402

【相似文獻(xiàn)】

相關(guān)期刊論文 前10條

1 錢曉寧,鄭戟,李征帆;小波多分辨率分析改進(jìn)互連結(jié)構(gòu)電容提取[J];電子學(xué)報(bào);1999年05期

2 Kathleen Nargi-Toth;Pradeep Gandhi;丁志廉;;高密度互連結(jié)構(gòu)[J];印制電路信息;2000年12期

3 朱震海，洪偉;超大規(guī)模集成電路中互連結(jié)構(gòu)的邏輯模型[J];電子學(xué)報(bào);1997年02期

4 鄭戟,李征帆;高速集成電路三維互連結(jié)構(gòu)電容參數(shù)的多重網(wǎng)格法提取[J];上海交通大學(xué)學(xué)報(bào);1998年04期

5 鄭戟,李征帆;高速電路中三維互連結(jié)構(gòu)頻變電感參數(shù)的提取[J];上海交通大學(xué)學(xué)報(bào);1999年01期

6 邵振海,洪偉;三維多導(dǎo)體互連結(jié)構(gòu)交擾問(wèn)題的時(shí)域分析[J];電子學(xué)報(bào);2000年02期

7 劉心松 ,彭壽全;分布式，

本文編號(hào)：2181361