低功耗復(fù)合邏輯門設(shè)計(jì)
發(fā)布時(shí)間：2018-08-13 15:07
【摘要】：隨著半導(dǎo)體工藝進(jìn)入深亞微米階段以及CMOS集成電路技術(shù)的發(fā)展,集成電路的工作頻率和集成度不斷提高,功耗問題日益演變成超大規(guī)模電路設(shè)計(jì)的瓶頸。在集成電路設(shè)計(jì)中,復(fù)雜的邏輯功能可以通過調(diào)用邏輯門來實(shí)現(xiàn)。但研究發(fā)現(xiàn),如將多個(gè)基本門組合產(chǎn)生的邏輯功能由單個(gè)復(fù)合門來替換往往可以實(shí)現(xiàn)電路性能的提升。這些復(fù)合門可以根據(jù)其邏輯功能,重新從晶體管級(jí)進(jìn)行設(shè)計(jì),運(yùn)用多種設(shè)計(jì)方法,從而達(dá)到減小面積和改善功能的目的。本論文重點(diǎn)研究了低功耗的復(fù)合門電路設(shè)計(jì),并對(duì)其在現(xiàn)實(shí)環(huán)境下的性能進(jìn)行了詳盡的闡述以及結(jié)果的對(duì)比分析。論文的研究工作主要包含了以下三個(gè)部分:1.對(duì)具有傳統(tǒng)布爾邏輯(Traditional Boolean,TB)的復(fù)合邏輯門設(shè)計(jì)的討論。針對(duì)目前布爾邏輯大多只利用了基礎(chǔ)單元的“與非”、“非”和“或非”等邏輯的單元電路來實(shí)現(xiàn)大規(guī)模電路的設(shè)計(jì),這樣的設(shè)計(jì)雖然取用單元電路方便,但也存在取用的單元電路數(shù)量多,面積大的缺陷。與傳統(tǒng)的單元電路級(jí)聯(lián)而成的基于TB邏輯復(fù)合門電路相比,基于晶體管級(jí)設(shè)計(jì)的電路擁有更小的面積和功耗。2.具有Reed-Muller(RM)邏輯的復(fù)合邏輯門單元電路的設(shè)計(jì)研究。針對(duì)現(xiàn)有RM邏輯,如三輸入“或/同或”,“異或/與”,在集成電路中以兩個(gè)二輸入門電路級(jí)聯(lián)形式出現(xiàn),導(dǎo)致功耗大、延時(shí)長(zhǎng)的不足,提出一種基于晶體管級(jí)復(fù)合邏輯門電路結(jié)構(gòu)的設(shè)計(jì)方案。該電路通過采用多軌結(jié)構(gòu)、縮短傳輸路徑,以及混合CMOS邏輯等設(shè)計(jì)方法,來克服原有電路中單一邏輯和單軌結(jié)構(gòu)信號(hào)路徑長(zhǎng)的不足,進(jìn)而提高電路性能。在55nm的CMOS技術(shù)工藝和PTM多種工藝下,經(jīng)過HSPICE模擬和Cadence提取版圖的后仿真,所設(shè)計(jì)的電路具有正確的邏輯功能,相較于采用門電路級(jí)聯(lián)而成的復(fù)合門電路,在不同負(fù)載、頻率和PVT組合等情況下的延時(shí)、功耗和功耗延遲積(PDP)都得到了明顯的改善。3.電路性能的測(cè)試環(huán)境設(shè)置及測(cè)量方法。在一些電路的性能比較中,設(shè)計(jì)者給出的測(cè)試方法往往并不能全面地反映電路的性能。本文在研究各電路的比較方式和方法后,提出給出一種相對(duì)公平的電路測(cè)試參考方案。
[Abstract]:With the development of semiconductor technology in deep submicron stage and CMOS integrated circuit technology, the working frequency and integration level of integrated circuit are increasing, and the power consumption problem is becoming the bottleneck of very large scale circuit design day by day. In integrated circuit design, complex logic function can be realized by calling logic gate. However, it is found that if the logic function generated by the combination of multiple basic gates is replaced by a single composite gate, the performance of the circuit can be improved. These composite gates can be redesigned from the transistor level according to their logic functions, and various design methods can be used to reduce the area and improve the function. This paper focuses on the design of low power compound gate circuit, and gives a detailed description of its performance in the real environment and a comparative analysis of the results. The research work of this paper mainly includes the following three parts: 1. The design of composite logic gates with traditional Boolean logic (Traditional Boolean terabytes) is discussed. At present, most Boolean logic uses only the cell circuits of the basic unit such as "and not", "not" and "or not" to realize the design of large-scale circuits. However, there are many cell circuits and large area defects. Compared with the traditional circuit cascaded based on TB logic gate, the transistor level circuit has a smaller area and power consumption. Research on the Design of compound Logic Gate Circuit with Reed-Muller (RM) Logic. For existing RM logic, such as three-input "or / or", "XOR / and", in the integrated circuit as two two-input gate circuit cascaded form, resulting in high power consumption, long delay, A design scheme based on transistor-level compound logic gate structure is presented. The circuit adopts multi-track structure, shortens the transmission path, and uses mixed CMOS logic to overcome the shortcomings of single logic and monorail structure signal path length in the original circuit, thereby improving the circuit performance. Under the CMOS technology and PTM technology of 55nm, after HSPICE simulation and post-simulation of Cadence extraction layout, the designed circuit has the correct logic function, compared with the composite gate circuit which is cascaded by gate circuit, it is under different loads. In the case of frequency and PVT combination, delay, power consumption and power delay product (PDP) are significantly improved. 3. Setting up test environment and measuring method of circuit performance. In the performance comparison of some circuits, the test methods given by the designers often do not reflect the performance of the circuits comprehensively. After studying the comparison methods of each circuit, a relatively fair circuit test reference scheme is proposed in this paper.
【學(xué)位授予單位】：寧波大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN791
[Abstract]:With the development of semiconductor technology in deep submicron stage and CMOS integrated circuit technology, the working frequency and integration level of integrated circuit are increasing, and the power consumption problem is becoming the bottleneck of very large scale circuit design day by day. In integrated circuit design, complex logic function can be realized by calling logic gate. However, it is found that if the logic function generated by the combination of multiple basic gates is replaced by a single composite gate, the performance of the circuit can be improved. These composite gates can be redesigned from the transistor level according to their logic functions, and various design methods can be used to reduce the area and improve the function. This paper focuses on the design of low power compound gate circuit, and gives a detailed description of its performance in the real environment and a comparative analysis of the results. The research work of this paper mainly includes the following three parts: 1. The design of composite logic gates with traditional Boolean logic (Traditional Boolean terabytes) is discussed. At present, most Boolean logic uses only the cell circuits of the basic unit such as "and not", "not" and "or not" to realize the design of large-scale circuits. However, there are many cell circuits and large area defects. Compared with the traditional circuit cascaded based on TB logic gate, the transistor level circuit has a smaller area and power consumption. Research on the Design of compound Logic Gate Circuit with Reed-Muller (RM) Logic. For existing RM logic, such as three-input "or / or", "XOR / and", in the integrated circuit as two two-input gate circuit cascaded form, resulting in high power consumption, long delay, A design scheme based on transistor-level compound logic gate structure is presented. The circuit adopts multi-track structure, shortens the transmission path, and uses mixed CMOS logic to overcome the shortcomings of single logic and monorail structure signal path length in the original circuit, thereby improving the circuit performance. Under the CMOS technology and PTM technology of 55nm, after HSPICE simulation and post-simulation of Cadence extraction layout, the designed circuit has the correct logic function, compared with the composite gate circuit which is cascaded by gate circuit, it is under different loads. In the case of frequency and PVT combination, delay, power consumption and power delay product (PDP) are significantly improved. 3. Setting up test environment and measuring method of circuit performance. In the performance comparison of some circuits, the test methods given by the designers often do not reflect the performance of the circuits comprehensively. After studying the comparison methods of each circuit, a relatively fair circuit test reference scheme is proposed in this paper.
【學(xué)位授予單位】：寧波大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN791
【相似文獻(xiàn)】
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