流水線型ADC確定性后臺(tái)校正系統(tǒng)研究與設(shè)計(jì)
發(fā)布時(shí)間：2018-08-13 09:29
【摘要】：模數(shù)轉(zhuǎn)換器(Analog-to-Digital Converter,ADC)在混合信號(hào)系統(tǒng)中起到將外界模擬信號(hào)轉(zhuǎn)換為數(shù)字信號(hào)的特殊作用。流水線型ADC作為中高速ADC的代表,能對(duì)速度、精度和功耗很好地折中,在很多領(lǐng)域都有廣泛應(yīng)用。所以它一直是模擬/混合信號(hào)集成電路中的研究熱點(diǎn)。隨著集成電路工藝的進(jìn)步,數(shù)字電路飛速發(fā)展,而模擬集成電路的發(fā)展卻相對(duì)滯后,ADC也就成了限制混合信號(hào)系統(tǒng)發(fā)展的瓶頸。數(shù)字校正技術(shù)的出現(xiàn)以及廣泛應(yīng)用使得ADC設(shè)計(jì)中對(duì)模擬信號(hào)的精度要求轉(zhuǎn)向數(shù)字域。該技術(shù)能緩和電源電壓降低和晶體管本征增益下降對(duì)ADC中模擬電路設(shè)計(jì)的影響,并且在實(shí)現(xiàn)高精度ADC的同時(shí)顯著降低ADC功耗。與常規(guī)的數(shù)字輔助校正ADC采用開(kāi)環(huán)工作方式的簡(jiǎn)單放大器代替?zhèn)鹘y(tǒng)的閉環(huán)運(yùn)放不同,本文采用了電流效率更高的推挽共源運(yùn)放。對(duì)低增益推挽共源運(yùn)放引入的高階非線性誤差,本文采用對(duì)運(yùn)放傳輸函數(shù)建立精確模型的方式進(jìn)行消除。該校正算法首先在流水線子級(jí)中引入校正子DAC,通過(guò)周期性地向校正子DAC注入數(shù)字測(cè)試信號(hào)獲得建模所需的插值端點(diǎn),然后采用分段的三階多項(xiàng)式擬合出運(yùn)放傳輸函數(shù)曲線。針對(duì)工藝限制引入的電容匹配誤差,本文又采用Karanicolas技術(shù)進(jìn)行校正。為了驗(yàn)證這種算法的校正效果,本文設(shè)計(jì)了12位分辨率,10M采樣率的流水線型ADC核心電路,其中第1-4級(jí)子級(jí)采用推挽共源運(yùn)放作為級(jí)間運(yùn)算放大器。ADC核心電路和數(shù)字校正算法混合仿真的結(jié)果表明,ADC的DNL和INL分別從校正前的(-1~1.75)LSB和(-7.9~7.6)LSB提高到校正后的(-0.75~0.5)LSB和(-0.9~1.2)LSB。對(duì)于4.88MHz的正弦測(cè)試信號(hào),SFDR和SNDR分別由校正前的44.3d B和38.8d B提高到校正后的82.0d B和70.7d B。校正后ADC的有效位數(shù)從6.2位提高到了11.5位。該ADC的總功耗為89.5m W,數(shù)字電路占總功耗的10.0%。同時(shí),該校正算法只需要11264個(gè)采樣周期即可完成所有校正參數(shù)估計(jì),具有收斂時(shí)間短的特點(diǎn)。
[Abstract]:Analog-to-Digital converter plays a special role in converting external analog signal into digital signal in mixed signal system. Pipelined ADC, as the representative of medium and high speed ADC, can make a good compromise on speed, precision and power consumption, and has been widely used in many fields. Therefore, it has always been the research hotspot in analog / mixed signal integrated circuits. With the progress of integrated circuit technology, digital circuits are developing rapidly, but the development of analog integrated circuits is relatively lagging behind ADC has become a bottleneck limiting the development of mixed signal systems. With the emergence and wide application of digital correction technology, the precision of analog signal in ADC design is changed to digital domain. This technique can alleviate the influence of the decrease of power supply voltage and transistor intrinsic gain on the design of analog circuits in ADC, and reduce the power consumption of ADC while realizing high precision ADC. Different from the conventional digital auxiliary correction (ADC), which uses a simple amplifier with open loop operation mode instead of the traditional closed-loop operational amplifier, this paper uses a push-pull common-source operational amplifier with higher current efficiency. The high order nonlinear error caused by low gain push-pull common-source operational amplifier is eliminated by establishing an accurate model of the transmission function of the amplifier. The correct algorithm first introduces the corrector DAC into the pipeline sublevel and periodically injects the digital test signal into the corrector DAC to obtain the interpolation endpoint needed for modeling. Then the piecewise third-order polynomial is used to fit the operational amplifier transfer function curve. Aiming at the capacitance matching error caused by process limitation, Karanicolas technique is used to correct the error. In order to verify the correction effect of this algorithm, a pipelined ADC core circuit with 12 bit resolution and 10 M sampling rate is designed. In the 1-4 sub-stage, the push-pull common-source operation amplifier is used as the core circuit of the interstage operational amplifier. The simulation results show that the DNL and INL of the ADC are improved from (-1) 1.75 LSB and (-7.97. 6) LSB before correction to (-0.75 ~ 0.5) LSB and (-0.91.2) LSBs after correction, respectively. SFDR and SNDR for 4.88MHz are increased from 44.3 dB and 38.8 dB before correction to 82.0 dB and 70.7 dB after correction, respectively. After correction, the effective bit number of ADC is increased from 6.2 bit to 11.5 bit. The total power consumption of the ADC is 89.5m W, and the digital circuit accounts for 10.0% of the total power consumption. At the same time, it only needs 11264 sampling periods to estimate all the corrected parameters, which has the advantage of short convergence time.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN792
本文編號(hào)：2180574
[Abstract]:Analog-to-Digital converter plays a special role in converting external analog signal into digital signal in mixed signal system. Pipelined ADC, as the representative of medium and high speed ADC, can make a good compromise on speed, precision and power consumption, and has been widely used in many fields. Therefore, it has always been the research hotspot in analog / mixed signal integrated circuits. With the progress of integrated circuit technology, digital circuits are developing rapidly, but the development of analog integrated circuits is relatively lagging behind ADC has become a bottleneck limiting the development of mixed signal systems. With the emergence and wide application of digital correction technology, the precision of analog signal in ADC design is changed to digital domain. This technique can alleviate the influence of the decrease of power supply voltage and transistor intrinsic gain on the design of analog circuits in ADC, and reduce the power consumption of ADC while realizing high precision ADC. Different from the conventional digital auxiliary correction (ADC), which uses a simple amplifier with open loop operation mode instead of the traditional closed-loop operational amplifier, this paper uses a push-pull common-source operational amplifier with higher current efficiency. The high order nonlinear error caused by low gain push-pull common-source operational amplifier is eliminated by establishing an accurate model of the transmission function of the amplifier. The correct algorithm first introduces the corrector DAC into the pipeline sublevel and periodically injects the digital test signal into the corrector DAC to obtain the interpolation endpoint needed for modeling. Then the piecewise third-order polynomial is used to fit the operational amplifier transfer function curve. Aiming at the capacitance matching error caused by process limitation, Karanicolas technique is used to correct the error. In order to verify the correction effect of this algorithm, a pipelined ADC core circuit with 12 bit resolution and 10 M sampling rate is designed. In the 1-4 sub-stage, the push-pull common-source operation amplifier is used as the core circuit of the interstage operational amplifier. The simulation results show that the DNL and INL of the ADC are improved from (-1) 1.75 LSB and (-7.97. 6) LSB before correction to (-0.75 ~ 0.5) LSB and (-0.91.2) LSBs after correction, respectively. SFDR and SNDR for 4.88MHz are increased from 44.3 dB and 38.8 dB before correction to 82.0 dB and 70.7 dB after correction, respectively. After correction, the effective bit number of ADC is increased from 6.2 bit to 11.5 bit. The total power consumption of the ADC is 89.5m W, and the digital circuit accounts for 10.0% of the total power consumption. At the same time, it only needs 11264 sampling periods to estimate all the corrected parameters, which has the advantage of short convergence time.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN792
【參考文獻(xiàn)】
相關(guān)期刊論文 前1條
1 殷秀梅;魏琦;許萊;楊華中;;A low power 12-b 40-MS/s pipeline ADC[J];半導(dǎo)體學(xué)報(bào);2010年03期
，本文編號(hào)：2180574
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