【摘要】：隨著工藝技術(shù)不斷創(chuàng)新,集成電路核心器件MOSFET的特征尺寸已縮小到深納米量級(jí),器件和集成芯片的性能都得到大幅提升。然而,深納米工藝代精細(xì)的版圖布局引入各類鄰近效應(yīng),深納米MOSFET器件性能因此產(chǎn)生波動(dòng),導(dǎo)致集成芯片的性能參數(shù)誤差及可靠性隱患。精確的MOSFET器件模型是集成電路設(shè)計(jì)和工藝之間的橋梁,目前國(guó)內(nèi)MOSFET版圖鄰近效應(yīng)模型的缺失為降低電路設(shè)計(jì)仿真誤差帶來(lái)難度。因此,建立準(zhǔn)確表征版圖鄰近效應(yīng)的MOSFET器件模型,對(duì)深納米工藝代中各類鄰近效應(yīng)做出精準(zhǔn)描述和預(yù)測(cè),對(duì)器件制造和電路仿真都有著重要的意義。本文首先從亞波長(zhǎng)光刻、應(yīng)力鄰近、高能離子注入和瞬態(tài)增強(qiáng)擴(kuò)散效應(yīng)四個(gè)方面,分析了版圖鄰近效應(yīng)的產(chǎn)生機(jī)理,研究確定了該效應(yīng)對(duì)器件性能的影響主要表現(xiàn)在閾值電壓Vth和相關(guān)電流的波動(dòng),因此選用緊湊模型委員會(huì)(CMC)認(rèn)證的基于閾值電壓的緊湊模型BSIM4.5作為核心模型,并對(duì)其擴(kuò)展實(shí)現(xiàn)版圖鄰近模型。本文基于國(guó)有先進(jìn)的40nm 1.1V MOSFET工藝平臺(tái),對(duì)從長(zhǎng)溝至短溝的130個(gè)NMOSFET和PMOSFET進(jìn)行流片和電學(xué)性能測(cè)試,完成了基于BSIM4.5的MOSFET C-V、I-V核心模型參數(shù)提取工作。MOSFET核心模型的提取結(jié)果表明,平均誤差小于2%,最大誤差小于5%,符合業(yè)界模型提取的標(biāo)準(zhǔn)。由于BSIM4.5模型涉及的版圖鄰近因子不全面,本文在MOSFET核心模型提取的基礎(chǔ)上,結(jié)合40nm MOSFET工藝的精細(xì)版圖,對(duì)STI應(yīng)力鄰近因子、阱鄰近因子、有源區(qū)鄰近因子和柵極鄰近因子這四類版圖鄰近因子,分別建立版圖鄰近子模型。在版圖鄰近子模型中,本文著重考慮11個(gè)版圖鄰近因子,新添加KSODXU0、 KSODXVTH0等28個(gè)模型參數(shù)以建立40nm MOSFET器件性能波動(dòng)與不同版圖鄰近因子相關(guān)性的物理表達(dá)式。通過(guò)對(duì)MOSFET核心模型中閾值電壓表達(dá)式Vth和遷移率表達(dá)式μeff的修正,將版圖鄰近子模型移植到MOSFET核心模型上,完成了版圖鄰近效應(yīng)模型的建立。為了對(duì)建立的版圖鄰近效應(yīng)模型進(jìn)行驗(yàn)證,本文通過(guò)對(duì)392個(gè)NMOSFET和PMOSFET測(cè)試結(jié)構(gòu)的參數(shù)測(cè)試和模型比對(duì),有效涵蓋大尺寸、短溝道、窄溝道和小尺寸器件,表明本文建立的版圖鄰近效應(yīng)模型實(shí)現(xiàn)了MOSFET 1-1mV的閾值電壓變化量和0.5-4.5%的漏電流變化率的模擬,有效降低電路設(shè)計(jì)中的仿真誤差。本文建立的40nm MOSFET版圖鄰近效應(yīng)模型能夠準(zhǔn)確擬合MOSFET的電學(xué)性能,具有較好的可讀性和可移植性,可實(shí)現(xiàn)更精準(zhǔn)的電路設(shè)計(jì)和性能仿真預(yù)測(cè)。
[Abstract]:With the continuous innovation of process technology, the characteristic size of integrated circuit core device (MOSFET) has been reduced to deep nanoscale order, and the performance of device and integrated chip has been greatly improved. However, various proximity effects are introduced into the precise layout of deep nanotechnology, which leads to the fluctuation of the performance of deep nanometer MOSFET devices, which leads to the error of performance parameters and the hidden trouble of reliability of the integrated chip. Accurate MOSFET device model is a bridge between integrated circuit design and process. At present, the lack of proximity effect model of MOSFET layout makes it difficult to reduce the circuit design simulation error. Therefore, it is of great significance for device manufacturing and circuit simulation to establish an accurate MOSFET device model to describe and predict all kinds of proximity effects in deep nanotechnology. In this paper, the mechanism of the proximity effect is analyzed from four aspects: subwavelength lithography, stress proximity, high energy ion implantation and transient enhanced diffusion. It is determined that the effect of this effect on the device performance is mainly due to the fluctuation of threshold voltage (Vth) and associated current. Therefore, a compact model based on threshold voltage (BSIM4.5), which is certified by the Compact Model Committee (CMC), is chosen as the core model. And the expansion of the layout of the adjacent model. Based on the state owned advanced 40nm 1.1 V MOSFET process platform, 130 NMOSFET and PMOSFET from long ditch to short ditch were tested for flow sheet and electrical properties. The extraction results of MOSFET C-V I-V core model based on BSIM4.5. The average error is less than 2 and the maximum error is less than 5. Because the proximity factor of BSIM4.5 model is not comprehensive, based on the extraction of MOSFET core model and the fine layout of 40nm MOSFET process, the STI stress proximity factor and well proximity factor are studied. The proximity factor of active region and the proximity factor of grid are four kinds of proximity factors of layout, and the adjacent submodels of layout are established respectively. In this paper, we focus on the consideration of 11 layout proximity factors and 28 model parameters, such as KSODXU0, KSODXVTH0, etc., in order to establish the physical expression of the correlation between the performance fluctuation of 40nm MOSFET devices and the adjacent factors of different layouts. By modifying the threshold voltage expression Vth and the mobility expression 渭 eff in the MOSFET core model, the layout proximity submodel is transplanted to the MOSFET core model, and the layout proximity effect model is established. In order to verify the layout proximity effect model, through the parameter test and model comparison of 392 NMOSFET and PMOSFET test structures, this paper effectively covers large size, short channel, narrow channel and small size devices. It is shown that the proposed layout proximity effect model can simulate the threshold voltage variation of MOSFET 1-1mV and the leakage current change rate of 0.5-4.5%, which can effectively reduce the simulation error in circuit design. The proximity effect model of 40nm MOSFET layout established in this paper can accurately fit the electrical properties of MOSFET. It has better readability and portability, and can realize more accurate circuit design and performance simulation prediction.
【學(xué)位授予單位】：華東師范大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN386

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