面向多核陣列的高速互連結(jié)構(gòu)設(shè)計與實現(xiàn)
發(fā)布時間：2018-08-12 12:22
【摘要】：隨著集成電路密度的提高,系統(tǒng)中各個組件的復(fù)雜度急劇增大,為了應(yīng)對不斷增加的晶體管密度、更高的時鐘頻率、更低的功耗以及面向市場的壓力,半導(dǎo)體行業(yè)將注意力從單芯片單處理器轉(zhuǎn)移到單芯片多處理器和多芯片多處理器。目前的多處理器大多通過總線方式互聯(lián),然而,當(dāng)處理單元數(shù)量增大到一定規(guī)模后,系統(tǒng)設(shè)計人員在設(shè)計互聯(lián)結(jié)構(gòu)時可能面臨前所未有的挑戰(zhàn),以往基于總線的設(shè)計方法由于不可避免的存在數(shù)據(jù)沖突,缺乏可擴展性和可預(yù)測性,不能滿足未來多核系統(tǒng)在性能、功率、時序收斂和擴展性等方面的發(fā)展需求。因此設(shè)計一個高效的高速互連結(jié)構(gòu)是多核處理系統(tǒng)設(shè)計的一個關(guān)鍵。論文設(shè)計了面向多核陣列的高速互聯(lián)結(jié)構(gòu),并在硬件平臺上進行了實現(xiàn)。多核陣列高速互連結(jié)構(gòu)主要采用片上網(wǎng)絡(luò)的方式進行互聯(lián),在跨越芯片和跨越板卡時我們采用高速串行接口進行數(shù)據(jù)轉(zhuǎn)換,以擴展多核的規(guī)模。論文首先研究了高速互連接口,介紹了高速互連接口中的幾個核心技術(shù),如串并轉(zhuǎn)換、數(shù)據(jù)編碼、時鐘恢復(fù)、數(shù)據(jù)同步等,并基于硬件平臺利用IBERT給出了測試Xilinx高速接口的步驟和測試結(jié)果,結(jié)果表明高速串行通道的誤碼率優(yōu)于8 E-14,同時給出了自定協(xié)議測試和SRIO協(xié)議測試結(jié)果,測試通過。接著研究了NoC,對比了路由協(xié)議、交換結(jié)構(gòu)、可靠性等核心部件,選擇了性能和實現(xiàn)復(fù)雜度折中的方案,并給出了對應(yīng)的硬件設(shè)計方案,從NI設(shè)計到路由器設(shè)計,從幀格式定義緩存大小的計算。然后給出了片內(nèi)NoC和片間高速串行通道互聯(lián)的實現(xiàn)方案,并利用SRIO通道和光通道拉通了PC和FPGA之間的雙向通道,實現(xiàn)了數(shù)據(jù)的采集和分發(fā),并在硬件平臺上拉通了整個設(shè)計�；谠O(shè)計出的多核平臺,將LTE-A無線通信系統(tǒng)基站側(cè)的基帶處理映射到多核平臺上,并完成了CoMP測試,最后基于32核的矢量處理器系統(tǒng),測試了交換能力,結(jié)果表明搭建的系統(tǒng)達到項目指標(biāo)要求。
[Abstract]:With the increasing density of integrated circuits, the complexity of each component in the system increases dramatically. In order to cope with the increasing density of transistors, higher clock frequency, lower power consumption and market-oriented pressure, The semiconductor industry shifts attention from single-chip single-processor to single-chip multi-processor and multi-chip multi-processor. At present, most multiprocessors are interconnected by bus. However, when the number of processing units increases to a certain scale, system designers may face unprecedented challenges in designing interconnected structures. Because of the inevitable data conflict and the lack of scalability and predictability, the previous design methods based on bus can not meet the development needs of future multi-core systems in terms of performance, power, timing convergence and scalability. Therefore, the design of an efficient high-speed interconnection structure is a key to the design of multi-core processing system. A high-speed interconnection architecture for multi-core array is designed and implemented on the hardware platform. Multi-core array high speed interconnection architecture mainly uses the mode of on-chip network to interconnect. In order to expand the scale of multi-core, we use high-speed serial interface for data conversion when we span chips and boards. This paper first studies the high speed interconnect interface, and introduces several core technologies in the high speed interconnection interface, such as serial-parallel conversion, data coding, clock recovery, data synchronization and so on. Based on the hardware platform, the steps and test results of testing Xilinx high-speed interface are given by using IBERT. The results show that the bit error rate of high-speed serial channel is better than that of 8E-14. Meanwhile, the test results of self-determined protocol and SRIO protocol are given, and the test results are passed. Then the paper studies Noc, compares the core components such as routing protocol, switching structure, reliability and so on, selects the compromise scheme of performance and implementation complexity, and gives the corresponding hardware design scheme, from NI design to router design. The calculation of the cache size defined from the frame format. Then, the scheme of interconnecting NoC and high-speed serial channels between chips is given, and the two-way channel between PC and FPGA is pulled through by using SRIO channel and optical channel. The data collection and distribution are realized, and the whole design is pulled through on the hardware platform. Based on the designed multi-core platform, the baseband processing of the base station side of LTE-A wireless communication system is mapped to the multi-core platform, and the CoMP test is completed. Finally, the switching ability is tested based on the 32-core vector processor system. The results show that the system meets the project requirements.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TN402
本文編號：2179042
[Abstract]:With the increasing density of integrated circuits, the complexity of each component in the system increases dramatically. In order to cope with the increasing density of transistors, higher clock frequency, lower power consumption and market-oriented pressure, The semiconductor industry shifts attention from single-chip single-processor to single-chip multi-processor and multi-chip multi-processor. At present, most multiprocessors are interconnected by bus. However, when the number of processing units increases to a certain scale, system designers may face unprecedented challenges in designing interconnected structures. Because of the inevitable data conflict and the lack of scalability and predictability, the previous design methods based on bus can not meet the development needs of future multi-core systems in terms of performance, power, timing convergence and scalability. Therefore, the design of an efficient high-speed interconnection structure is a key to the design of multi-core processing system. A high-speed interconnection architecture for multi-core array is designed and implemented on the hardware platform. Multi-core array high speed interconnection architecture mainly uses the mode of on-chip network to interconnect. In order to expand the scale of multi-core, we use high-speed serial interface for data conversion when we span chips and boards. This paper first studies the high speed interconnect interface, and introduces several core technologies in the high speed interconnection interface, such as serial-parallel conversion, data coding, clock recovery, data synchronization and so on. Based on the hardware platform, the steps and test results of testing Xilinx high-speed interface are given by using IBERT. The results show that the bit error rate of high-speed serial channel is better than that of 8E-14. Meanwhile, the test results of self-determined protocol and SRIO protocol are given, and the test results are passed. Then the paper studies Noc, compares the core components such as routing protocol, switching structure, reliability and so on, selects the compromise scheme of performance and implementation complexity, and gives the corresponding hardware design scheme, from NI design to router design. The calculation of the cache size defined from the frame format. Then, the scheme of interconnecting NoC and high-speed serial channels between chips is given, and the two-way channel between PC and FPGA is pulled through by using SRIO channel and optical channel. The data collection and distribution are realized, and the whole design is pulled through on the hardware platform. Based on the designed multi-core platform, the baseband processing of the base station side of LTE-A wireless communication system is mapped to the multi-core platform, and the CoMP test is completed. Finally, the switching ability is tested based on the 32-core vector processor system. The results show that the system meets the project requirements.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TN402
【參考文獻】
相關(guān)期刊論文 前1條
1 陳書明;萬江華;魯建壯;劉仲;孫海燕;孫永節(jié);劉衡竹;劉祥遠;李振濤;徐毅;陳小文;;YHFT-QDSP:High-Performance Heterogeneous Multi-Core DSP[J];Journal of Computer Science & Technology;2010年02期
，本文編號：2179042
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