【摘要】：生物安全是指生物性的傳染媒介通過(guò)直接感染或間接破壞環(huán)境而導(dǎo)致對(duì)人類、動(dòng)物或植物的直接或潛在的威脅。通過(guò)研究發(fā)現(xiàn),傳染媒介大部分是由微生物引起的。由于微生物種類繁多,且容易發(fā)生突變,在面對(duì)突發(fā)生物安全事件時(shí),需要迅速確定微生物的種類及來(lái)源,才能夠采取有效措施抑制傳染媒介的擴(kuò)散和發(fā)展,因此安全、可靠、快速、準(zhǔn)確的微生物檢測(cè)技術(shù)是生物安全領(lǐng)域中亟待解決的關(guān)鍵問(wèn)題之一。傳統(tǒng)微生物檢測(cè)技術(shù)具有易污染、周期長(zhǎng)、靈敏度低等特點(diǎn),而國(guó)外使用的基于微生物表達(dá)譜的生物質(zhì)譜分析技術(shù)可實(shí)現(xiàn)對(duì)微生物的現(xiàn)場(chǎng)快速、準(zhǔn)確的鑒定、分類、溯源和監(jiān)測(cè),具有傳統(tǒng)微生物檢測(cè)技術(shù)不可比擬的優(yōu)勢(shì),為生物安全等領(lǐng)域提供了一種強(qiáng)有力的分析測(cè)試手段,但對(duì)我國(guó)采取了核心技術(shù)封鎖策略,因此開發(fā)具有核心自主知識(shí)產(chǎn)權(quán)的創(chuàng)新微生物檢測(cè)設(shè)備和配套技術(shù)體系已成為我國(guó)生物安全領(lǐng)域研究的重要課題。本論文所研究的高速數(shù)據(jù)采集系統(tǒng)是國(guó)家重大科學(xué)儀器設(shè)備開發(fā)專項(xiàng)“生物安全專用基質(zhì)輔助激光解析儀的開發(fā)及應(yīng)用(2012YQ180117)”中的重要組成部分之一�；|(zhì)輔助激光解析電離化/飛行時(shí)間質(zhì)譜(MALDI-TOF-MS)是近年來(lái)快速發(fā)展起來(lái)的一種新型軟電離生物質(zhì)譜,具有靈敏度高、準(zhǔn)確度高及分辨率高等特點(diǎn)。MALDI-TOF-MS由進(jìn)樣系統(tǒng)、基質(zhì)輔助激光解析離子源、飛行時(shí)間質(zhì)量分析器和離子束流高速采集等幾部分組成。離子束流高速采集包括離子檢測(cè)器和高速數(shù)據(jù)采集系統(tǒng)兩部分,其中高速數(shù)據(jù)采集系統(tǒng)完成對(duì)檢測(cè)器輸出的離子脈沖信號(hào)的數(shù)據(jù)采集、傳輸、處理、分析等。準(zhǔn)確測(cè)量離子脈沖信號(hào)是獲得高質(zhì)量質(zhì)譜數(shù)據(jù)的關(guān)鍵環(huán)節(jié)。高頻微弱離子脈沖信號(hào)的測(cè)量包括微弱信號(hào)調(diào)理電路、高速ADC數(shù)據(jù)采集、數(shù)據(jù)存儲(chǔ)、數(shù)據(jù)上傳處理分析等。為提高離子脈沖信號(hào)測(cè)量精度,本文以FPGA作為主控芯片,利用過(guò)采樣技術(shù)提高信噪比,即將ADC采樣率設(shè)定為2Gsps,同時(shí)設(shè)定ADC分辨率為12bit,并配合數(shù)據(jù)采集傳輸擴(kuò)展相應(yīng)存儲(chǔ)容量和高速傳輸接口,實(shí)現(xiàn)對(duì)離子脈沖信號(hào)的快速、高精度測(cè)量。本論文的具體研究?jī)?nèi)容包括:1.高速數(shù)據(jù)采集系統(tǒng)方案設(shè)計(jì)。從滿足MALDI-TOF-MS中離子脈沖信號(hào)檢測(cè)要求出發(fā),首先確定了高速數(shù)據(jù)采集系統(tǒng)硬件電路構(gòu)成形式。該硬件電路主要包括FPGA主控電路、信號(hào)調(diào)理電路、ADC采樣電路、DDR2 SDRAM存儲(chǔ)電路、千兆以太網(wǎng)電路、ADC時(shí)鐘電路,及所需電源電路等。其中FPGA主控電路實(shí)現(xiàn)對(duì)整個(gè)高速數(shù)據(jù)采集系統(tǒng)的邏輯控制;信號(hào)調(diào)理電路主要對(duì)MALDI-TOF-MS檢測(cè)器輸出的最大幅值為10mA的離子脈沖信號(hào)進(jìn)行電流轉(zhuǎn)電壓、微弱信號(hào)放大、同時(shí)為與ADC輸入方式配合將信號(hào)由單端輸出轉(zhuǎn)為差分輸出;高速ADC模塊對(duì)調(diào)理輸出信號(hào)進(jìn)行高速采樣,將離子脈沖信號(hào)轉(zhuǎn)換成數(shù)字信號(hào);DDR2 SDRAM存儲(chǔ)電路實(shí)現(xiàn)對(duì)采樣數(shù)據(jù)的緩存,同時(shí)降低數(shù)據(jù)的實(shí)時(shí)傳輸速率。為提高被測(cè)樣品離子脈沖信號(hào)測(cè)量信噪比,需對(duì)同一樣品的多次離子脈沖信號(hào)采樣后進(jìn)行數(shù)據(jù)疊加處理,在FPGA內(nèi)部存儲(chǔ)空間無(wú)法滿足情況下,外擴(kuò)DDR2 SDRAM進(jìn)行數(shù)據(jù)緩存;千兆以太網(wǎng)電路主要以1000Mbps的速率實(shí)現(xiàn)與上位機(jī)的數(shù)據(jù)交互;ADC時(shí)鐘電路提供ADC芯片所需的高頻、高精度采樣時(shí)鐘;電源模塊主要是為高速數(shù)據(jù)采集系統(tǒng)提供所需要的電源。2.進(jìn)行高速數(shù)據(jù)采集系統(tǒng)硬件電路設(shè)計(jì)。從MALDI-TOF-MS所要檢測(cè)的離子脈沖寬度、測(cè)量精度、最大質(zhì)量數(shù)、疊加次數(shù)等參數(shù)確定高速數(shù)據(jù)采集系統(tǒng)采樣率為2Gsps、分辨率為12bit、離子脈沖信號(hào)有效帶寬在400MHz以內(nèi)、存儲(chǔ)容量為512MB,并通過(guò)千兆以太網(wǎng)口實(shí)現(xiàn)采樣數(shù)據(jù)的批量上傳。為提高采樣時(shí)鐘頻率精度,通過(guò)選取鎖相環(huán)芯片,生成ADC芯片所需要的1GHz差分時(shí)鐘;調(diào)理電路模塊所選芯片為具有超低噪聲和超低失真的運(yùn)算放大器AD8099,以及高帶寬差分放大器等實(shí)現(xiàn)高帶寬、高信噪比,且滿足ADC滿量程的輸出信號(hào)。為保證高速信號(hào)完整性,在電路布線與PCB制板時(shí)采取了如下具體措施:(1)對(duì)于高頻模擬信號(hào)和數(shù)字信號(hào)傳輸線,采用差分處理,有效降低噪聲,提高抗干擾能力;(2)在設(shè)計(jì)電路板時(shí)采用8層制板,即頂層-地層-信號(hào)層-電源層-地層-信號(hào)層-電源層-底層,使信號(hào)層與地層或電源層相鄰,保證信號(hào)返回路徑阻抗最小;(3)AD模塊采用100歐姆差分電阻進(jìn)行阻抗匹配,減小信號(hào)反射;(4)電源層、地層布線與信號(hào)布線的走線方向一致,減小噪聲干擾;(5)DDR2SDRAM模塊采用蛇形走線,保持信號(hào)長(zhǎng)度一致,滿足信號(hào)時(shí)序要求;(6)信號(hào)線間距采用3W原則,減小信號(hào)間串?dāng)_;(7)表層與底層做鋪地處理,以及為板卡制作法拉第電籠等,減小電磁干擾。通過(guò)以上措施,有效保證了信號(hào)完整性。3.FPGA邏輯設(shè)計(jì)。FPGA內(nèi)部邏輯設(shè)計(jì)主要包括ADC時(shí)鐘模塊控制邏輯、ADC高速輸出數(shù)據(jù)接口、DDR2 SDRAM控制器及其控制邏輯、千兆以太網(wǎng)芯片控制邏輯等。其中ADC時(shí)鐘模塊控制邏輯使FPGA芯片通過(guò)SPI接口控制鎖相環(huán)芯片生成1GHz時(shí)鐘,作為ADC芯片的采樣時(shí)鐘;ADC高速數(shù)據(jù)輸出接口主要在FPGA內(nèi)部例化一個(gè)輸入為48bit,輸出為32bit的異步FIFO,進(jìn)行數(shù)據(jù)位數(shù)轉(zhuǎn)換。DDR2 SDRAM控制器及其控制邏輯主要調(diào)用DDR2 SDRAM Controller with altmemphy IP核,通過(guò)控制邏輯控制IP核從而實(shí)現(xiàn)對(duì)DDR2 SDRAM的讀寫操作。千兆以太網(wǎng)控制邏輯主要編寫了UDP協(xié)議通過(guò)GMII接口實(shí)現(xiàn)數(shù)據(jù)的傳輸。通過(guò)FPGA邏輯控制,實(shí)現(xiàn)了高速數(shù)據(jù)采集系統(tǒng)時(shí)序和控制的協(xié)調(diào)統(tǒng)一。4.高速數(shù)據(jù)采集系統(tǒng)性能測(cè)試。鎖相環(huán)模塊、ADC模塊、存儲(chǔ)模塊和千兆以太網(wǎng)模塊是高速數(shù)據(jù)采集系統(tǒng)的核心部分,分別測(cè)試高速數(shù)據(jù)采集系統(tǒng)的信號(hào)采集、數(shù)據(jù)存儲(chǔ)和數(shù)據(jù)傳輸功能,具體結(jié)果包括:(1)以FPGA作為主控芯片,配合采樣率為2Gsps、分辨率為12bit的ADC芯片對(duì)高頻離子脈沖信號(hào)進(jìn)行高速高精度采樣。通過(guò)對(duì)250MHz輸入信號(hào)進(jìn)行實(shí)際采樣測(cè)試,達(dá)到SNR=44.6639,ENOB=7.1269,滿足設(shè)計(jì)要求;(2)以FPGA作為主控芯片,配合DDR2 SDRAM大容量存儲(chǔ)芯片對(duì)ADC采樣數(shù)據(jù)進(jìn)行高速實(shí)時(shí)存儲(chǔ),在傳輸速率為667Mbps下,傳輸數(shù)據(jù)準(zhǔn)確;(3)以FPGA作為主控芯片,配合千兆以太網(wǎng)接口實(shí)現(xiàn)對(duì)DDR2SDRAM中批量數(shù)據(jù)的高速上傳,在傳輸為1000Mbps下,傳輸數(shù)據(jù)準(zhǔn)確。此外,針對(duì)調(diào)理電路進(jìn)行測(cè)試,實(shí)現(xiàn)了有效帶寬在400MHz以內(nèi),且達(dá)到ADC芯片的滿量程輸入信號(hào),且信噪比較高,滿足設(shè)計(jì)要求。最后,對(duì)高速數(shù)據(jù)采集系統(tǒng)所涉及的研究工作進(jìn)行了總結(jié)。本論文主要依據(jù)MALDI-TOF-MS的指標(biāo)要求對(duì)數(shù)據(jù)采集系統(tǒng)進(jìn)行需求分析和具體設(shè)計(jì),并對(duì)高速數(shù)據(jù)采集系統(tǒng)板卡的核心功能和關(guān)鍵指標(biāo)進(jìn)行了測(cè)試驗(yàn)證,測(cè)試結(jié)果滿足設(shè)計(jì)要求。下一步研究計(jì)劃:1、通過(guò)完善硬件電路、軟件濾波等措施,進(jìn)一步提高調(diào)理電路和ADC采樣電路的信噪比,實(shí)現(xiàn)系統(tǒng)測(cè)量精度和測(cè)量靈敏度的進(jìn)一步提升。2、對(duì)已完成過(guò)的獨(dú)立邏輯設(shè)計(jì)進(jìn)行整合,實(shí)現(xiàn)高速數(shù)據(jù)采集系統(tǒng)從離子脈沖信號(hào)采集→數(shù)據(jù)存儲(chǔ)→數(shù)據(jù)傳輸?shù)耐暾鞒?為后續(xù)進(jìn)行數(shù)據(jù)處理分析并生成質(zhì)譜圖提供關(guān)鍵支撐。3、開發(fā)上位機(jī)數(shù)據(jù)解析處理算法,進(jìn)一步提高測(cè)量信號(hào)精度。4、在質(zhì)譜儀仿真平臺(tái)上,開展高速數(shù)據(jù)采集系統(tǒng)的應(yīng)用測(cè)試評(píng)價(jià)。
[Abstract]:Biosafety refers to the direct or potential threat to humans, animals or plants caused by biological vector through direct infection or indirect destruction of the environment. It has been found that most of the vector is caused by microorganisms. Only by quickly identifying the types and sources of microorganisms can effective measures be taken to inhibit the spread and development of infectious media. Therefore, safe, reliable, rapid and accurate microbial detection technology is one of the key problems in the field of biosafety. Biomass spectrometry based on microbial expression profiles, which is used abroad, can identify, classify, trace and monitor microorganisms quickly and accurately in the field. It has incomparable advantages over traditional microbial detection techniques, and provides a powerful analytical and testing means for Biosafety and other fields. However, it has adopted a core in China. Therefore, the development of innovative microbial detection equipment with core independent intellectual property rights and supporting technical systems has become an important issue in the field of biosafety in China. Matrix-assisted laser analytical ionization/time-of-flight mass spectrometry (MALDI-TOF-MS) is a new type of soft ionization mass spectrometry developed rapidly in recent years. It has the characteristics of high sensitivity, high accuracy and high resolution. Ion beam high-speed acquisition includes ion detector and high-speed data acquisition system, in which high-speed data acquisition system completes the data acquisition, transmission, processing and analysis of the ion pulse signal output by the detector. The measurement of high frequency weak ion pulse signal includes weak signal conditioning circuit, high speed ADC data acquisition, data storage, data upload processing and analysis. In order to improve the measurement accuracy of ion pulse signal, this paper uses FPGA as the main control chip and over sampling technology. To improve the signal-to-noise ratio, the ADC sampling rate is set to 2 Gsps, and the ADC resolution is set to 12 bits, and the corresponding storage capacity and high-speed transmission interface are expanded with the data acquisition and transmission to achieve rapid and high-precision measurement of the ion pulse signal. The specific research contents of this paper include: 1. High-speed data acquisition system design. In order to detect the ion pulse signal in TOF-MS, the hardware structure of the high-speed data acquisition system is firstly determined. The hardware circuit mainly includes the main control circuit of FPGA, signal conditioning circuit, ADC sampling circuit, DDR2 SDRAM storage circuit, Gigabit Ethernet circuit, ADC clock circuit and the power supply circuit needed. The logic control of the whole high-speed data acquisition system is realized; the signal conditioning circuit mainly converts the ionic pulse signal with the maximum output amplitude of 10 mA from MALDI-TOF-MS detector into a current-switching voltage, amplifies the weak signal, and converts the signal from single-ended output to differential output in conjunction with the ADC input mode; the high-speed ADC module converts the modulation output. The DDR2 SDRAM storage circuit realizes the caching of the sampled data and reduces the real-time transmission rate of the data. In order to improve the signal-to-noise ratio (SNR) of the ionic pulse signal measured by the sampled sample, it is necessary to sample the multiple ionic pulse signal of the same sample and superimpose the data after sampling. When the internal storage space of PGA is not enough, the external DDR2 SDRAM is used to buffer the data; the Gigabit Ethernet circuit mainly interacts with the host computer at 1000Mbps speed; the ADC clock circuit provides the high frequency and high precision sampling clock needed by the ADC chip; and the power module mainly provides the power needed for the high-speed data acquisition system. 2. Design the hardware circuit of the high-speed data acquisition system. The sampling rate of the high-speed data acquisition system is 2Gsps, the resolution is 12bit, the effective bandwidth of the ion pulse signal is within 400MHz, the storage capacity is 512MB, and the sampling rate is determined by the parameters of MALDI-TOF-MS. In order to improve the precision of sampling clock frequency, a phase-locked loop chip is selected to generate the 1GHz differential clock needed by ADC chip; the chip selected by the conditioning circuit module is an operational amplifier AD8099 with ultra-low noise and ultra-low distortion, and a high bandwidth differential amplifier. In order to ensure the integrity of high-speed signal, the following specific measures are taken in circuit wiring and PCB board making: (1) For high-frequency analog signal and digital signal transmission line, differential processing is used to effectively reduce noise and improve anti-interference ability; (2) Eight-layer board is used in circuit board design, that is, top-to-ground board. Layer-Signal Layer-Power Layer-Stratum-Signal Layer-Power Layer-Bottom Layer, so that the signal layer adjacent to the stratum or power layer, to ensure that the signal return path impedance is the smallest; (3) AD module using 100 ohm differential resistance impedance matching to reduce signal reflection; (4) power layer, stratum wiring and signal wiring alignment, reduce noise interference; (5) DDR2 SDRAM module adopts snake-like line to keep the length of signal consistent to meet the requirements of signal timing; (6) signal line spacing adopts the principle of 3W to reduce cross-talk between signals; (7) surface and bottom layers to do ground processing, as well as for the board card Faraday cage to reduce electromagnetic interference. Through the above measures, effectively ensure the integrity of the signal. 3. FPGA logic design. GA internal logic design mainly includes ADC clock module control logic, ADC high-speed output data interface, DDR2 SDRAM controller and its control logic, Gigabit Ethernet chip control logic and so on. The DDR2 SDRAM controller and its control logic call the DDR2 SDRAM Controller with altmemphy IP core, and control the IP core through the control logic to realize the read-write operation of DDR2 SDRAM. Gigabit Ethernet The control logic mainly compiles UDP protocol to realize data transmission through GMII interface. The timing and control of high-speed data acquisition system are coordinated and unified by FPGA logic control. 4. Performance test of high-speed data acquisition system. Phase-locked loop module, ADC module, storage module and Gigabit Ethernet module are the core of high-speed data acquisition system. In this part, the functions of signal acquisition, data storage and data transmission of high-speed data acquisition system are tested respectively. The specific results include: (1) High-speed and high-precision sampling of high-frequency ion pulse signal is carried out by using FPGA as the main control chip, cooperating with ADC chip with sampling rate of 2 Gsps and resolution of 12 bits. Trial, to achieve SNR = 44.6639, ENOB = 7.1269, to meet the design requirements; (2) FPGA as the main control chip, with DDR2 SDRAM large-capacity memory chip for high-speed real-time storage of ADC sampling data, in the transmission rate of 667 Mbps, accurate data transmission; (3) FPGA as the main control chip, with Gigabit Ethernet interface to achieve the DDR2 SDRAM batch data In addition, the effective bandwidth is within 400 MHz, and the full range input signal of ADC chip is achieved. The signal-to-noise ratio is high, which meets the design requirements. Finally, the research work of high-speed data acquisition system is summarized. According to the requirements of MALDI-TOF-MS, the data acquisition system is analyzed and designed, and the core functions and key indicators of the high-speed data acquisition system board are tested and verified. The test results meet the design requirements. The next research plan: 1. By improving the hardware circuit, software filtering and other measures to further improve The signal-to-noise ratio of conditioning circuit and ADC sampling circuit can further improve the measurement accuracy and sensitivity of the system. 2. Integrate the independent logic design which has been completed, realize the complete flow of high-speed data acquisition system from ion pulse signal acquisition to data storage to data transmission, and then carry on data processing and analysis for the follow-up. Mass spectrogram provides the key support. 3. Develop the upper computer data analysis and processing algorithm to further improve the measurement signal accuracy. 4. Develop the application test and evaluation of high-speed data acquisition system on the mass spectrometer simulation platform.
【學(xué)位授予單位】：中國(guó)人民解放軍軍事醫(yī)學(xué)科學(xué)院
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TH744.5

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相關(guān)期刊論文 前10條

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