本文選題：寬電壓 + PVT偏差��； 參考：《東南大學》2015年碩士論文

【摘要】：隨著集成電路技術(shù)的飛速發(fā)展,寬電壓電路由于能夠兼顧性能和能效兩大需求,受到廣泛關(guān)注。然而如何能夠在常規(guī)電壓區(qū)獲得高性能的同時盡量降低功耗,并且在低電壓近閾值區(qū)抑制PVT偏差的劇烈影響實現(xiàn)高能效成為了寬電壓設計的瓶頸。自適應電壓頻率調(diào)節(jié)(Adaptive Voltage Frequency Scaling, AVFS)技術(shù)可以利用片上監(jiān)控單元監(jiān)測關(guān)鍵路徑時序,并實時調(diào)節(jié)芯片的電壓、頻率,成為攻克寬電壓設計瓶頸的有力手段�？紤]到寬電壓、先進工藝下局部PVT偏差嚴重,綜合對比常用AVFS設計方法,本文主要研究在線監(jiān)測中預測型的AVFS技術(shù)。首先設計了一款延時可配的在線監(jiān)控單元以及一套靜態(tài)時序分析同動態(tài)時序仿真相結(jié)合的監(jiān)控點選取方法,并給出了在已完成流片的芯片上的實際應用效果：隨后,設計了AVFS控制模塊和以Cortex-M3為核心的小型SoC驗證電路,使用SMIC 40nm工藝完成了包括版圖在內(nèi)的前后端設計,其中AVFS部分引入了4.7%的面積開銷；最后設計了HSIM-VCS混合仿真平臺,對整個設計進行仿真驗證。仿真結(jié)果表明,在常規(guī)電壓(1.1V)區(qū),根據(jù)工藝角和溫度的不同,最好情況即FF工藝角、-25℃時有54.3%的功耗收益,即使最壞情況即SS工藝角、125℃也有28.5%的功耗收益：在低電壓近閩值(0.6V)區(qū),有效抑制PVT偏差對電路的影響之外,最高有73.2%的功耗收益。能效角度來看,開啟AVFS功能后,低電壓區(qū)較常規(guī)電壓區(qū)能效提高到3倍以上。對比國內(nèi)外相關(guān)研究,本文的寬電壓AVFS設計在有效抑制PVT偏差之外可以獲得顯著的功耗、能效收益。
[Abstract]:With the rapid development of integrated circuit (IC) technology, wide voltage circuits (WVCs) have attracted wide attention due to their ability to meet the requirements of both performance and energy efficiency. However, how to achieve high performance in conventional voltage range and reduce power consumption, and how to reduce the severe impact of PVT deviation in low voltage near threshold region and achieve high energy efficiency has become the bottleneck of wide voltage design. Adaptive Voltage Frequency scaling (Adaptive) technology can use on-chip monitoring unit to monitor critical path timing, and adjust the voltage and frequency of the chip in real time, which becomes a powerful means to overcome the bottleneck of wide voltage design. Considering the wide voltage and the serious local PVT deviation under advanced technology, this paper mainly studies the predictive AVFS technology in on-line monitoring, which is compared with the commonly used AVFS design methods. First of all, a delay and configurable on-line monitoring unit and a set of monitoring points selection method combining static timing analysis with dynamic timing simulation are designed, and the practical application results on the chip of the completed stream chip are given. The control module of AVFS and the verification circuit based on Cortex-M3 are designed. The design of front and rear end, including layout, is completed by using SMIC 40nm process, in which the area overhead is 4.7%. Finally, the hybrid simulation platform of HSIM-VCS is designed. The whole design is simulated and verified. The simulation results show that in the conventional voltage (1.1 V) region, according to the process angle and temperature, the best case is that the FF process angle at 25 鈩，

本文編號：2107691