本文選題：布局 + 三維集成電路�。� 參考：《國(guó)防科學(xué)技術(shù)大學(xué)》2015年碩士論文

【摘要】：隨著集成電路技術(shù)不斷發(fā)展,互連問(wèn)題成為影響芯片性能的瓶頸。三維集成電路技術(shù)提供給設(shè)計(jì)者一種全新的設(shè)計(jì)方式,能夠有效地縮短互連線長(zhǎng)、降低時(shí)序延遲、改善芯片性能,目前已成集成電路發(fā)展的新方向。在三維芯片設(shè)計(jì)過(guò)程中,布局是物理設(shè)計(jì)中重要的環(huán)節(jié),但是目前國(guó)際范圍內(nèi)還缺乏有效支持三維芯片設(shè)計(jì)的EDA工具,因此研究突破三維芯片布局技術(shù)對(duì)提高芯片的性能具有重要意義。與傳統(tǒng)二維芯片相比,三維芯片具有特殊的三維結(jié)構(gòu),因此三維芯片設(shè)計(jì)不能簡(jiǎn)單地照搬二維芯片的設(shè)計(jì)技術(shù),其布局問(wèn)題需要研究開發(fā)新的三維布局算法。本文結(jié)合國(guó)內(nèi)外布局算法研究動(dòng)態(tài),選取三維芯片布局技術(shù)作為研究方向。首先對(duì)國(guó)際物理設(shè)計(jì)會(huì)議提供的二維benchmark進(jìn)行研究,并且設(shè)計(jì)實(shí)現(xiàn)基于折疊的三維轉(zhuǎn)換方法,將二維benchmark轉(zhuǎn)換為三維benchmark,將其作為三維布局算法研究的基礎(chǔ)。然后設(shè)計(jì)實(shí)現(xiàn)一個(gè)基于劃分的三維布局器,完成三維芯片上的布局,并對(duì)布局結(jié)果的互連線長(zhǎng)進(jìn)行性能評(píng)估。結(jié)果表明:第一,相對(duì)于“Krafwerk”二維布局算法,基于劃分的三維布局器HPWL平均減少35.02%。第二,相對(duì)于基于折疊的三維布局器,基于劃分的三維布局器HPWL平均減少26.60%,運(yùn)行時(shí)間平均減少26.81%�；趧澐值娜S布局器的實(shí)現(xiàn)將會(huì)為我國(guó)自主研發(fā)三維芯片提供相應(yīng)的理論和技術(shù)支持。
[Abstract]:With the development of integrated circuit technology, interconnection becomes the bottleneck of chip performance. Three-dimensional integrated circuit technology provides designers with a new design method, which can effectively shorten the interconnection line length, reduce timing delay, improve chip performance, has become a new direction of integrated circuit development. In the process of 3D chip design, layout is an important part of physical design, but there is still a lack of EDA tools to support 3D chip design in the international scope. Therefore, it is important to research and break through the three-dimensional chip layout technology to improve the chip performance. Compared with traditional 2D chips, 3D chips have special 3D structure, so 3D chip design can not simply copy the design technology of 2D chips. The layout problem of 3D chips needs to be studied and developed. In this paper, three-dimensional chip layout technology is selected as the research direction, combined with the research trends of layout algorithms at home and abroad. Firstly, the 2D benchmark provided by the International physical Design Conference is studied, and the folding based 3D conversion method is designed and implemented. The 2D benchmark is converted to 3D benchmark, which is the basis of the research on 3D layout algorithm. Then we design and implement a 3D layout device based on partition to complete the layout of 3D chip and evaluate the performance of the interconnect length of the layout result. The results show that: first, compared with the "Krafwerk" two-dimensional layout algorithm, the average reduction of HPWL based on partition is 35.02. Second, compared with the folding based 3D layouts, the partition based 3D layouts reduce the average HPWL by 26.60 and the average running time by 26.81. The realization of 3D layout based on partition will provide corresponding theoretical and technical support for our own research and development of 3D chips.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN402

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本文編號(hào)：2107412