本文選題：中繼器插入 + 互連線延時(shí)�。� 參考：《國(guó)防科學(xué)技術(shù)大學(xué)》2015年碩士論文

【摘要】：集成電路工藝進(jìn)入到納米工藝之后,互連線成為影響電路延時(shí)的主導(dǎo)因素。為了保證芯片設(shè)計(jì)能夠達(dá)到時(shí)序收斂的目標(biāo),互連線的延時(shí)優(yōu)化就顯得格外重要,其中,中繼器插入方法是減小互連線延時(shí)最常用、最有效的方式之一。本文在40納米工藝下,以實(shí)際工程為依托,針對(duì)高性能微處理器芯片物理設(shè)計(jì)中的互連問題,對(duì)中繼器插入方法展開了以下研究工作。一、優(yōu)化點(diǎn)對(duì)點(diǎn)互連線延時(shí)的中繼器插入方法。本文對(duì)大量不同線長(zhǎng)和不同類型中繼器的組合進(jìn)行了中繼器插入方法的實(shí)驗(yàn)和分析。分析結(jié)果表明,隨著中繼器驅(qū)動(dòng)倍數(shù)的增大,相同長(zhǎng)度互連線的延時(shí)逐漸變小,但面積和功耗開銷隨之增大,綜合考慮延時(shí)、功耗和面積等開銷,較優(yōu)的互連線段長(zhǎng)度是200μm~300μm,較優(yōu)的中繼器類型是12倍驅(qū)動(dòng)的反相器單元。二、優(yōu)化全局互連總線延時(shí)的中繼器插入方法。本文針對(duì)模塊間的有限區(qū)域內(nèi)存在大量全局互連總線所引起的延時(shí)、串?dāng)_及擁塞問題,進(jìn)行了中繼器插入方法的優(yōu)化和評(píng)估,采用交錯(cuò)插入方式對(duì)中繼器位置進(jìn)行優(yōu)化,采用特殊布線規(guī)則對(duì)并行總線進(jìn)行優(yōu)化。實(shí)驗(yàn)分析結(jié)果表明,該方法有效地降低了局部擁塞和串?dāng)_,減小了全局互連線的延時(shí),將互連線的總延時(shí)和串?dāng)_分別降低了25.4%和21.8%。三、優(yōu)化多扇出互連網(wǎng)絡(luò)延時(shí)的中繼器插入方法。物理設(shè)計(jì)中存在一些多扇出互連網(wǎng)絡(luò),采用EDA工具自動(dòng)優(yōu)化可能引起插入的中繼器數(shù)量過多,從而導(dǎo)致局部單元密度過高及擁塞問題。本文提出一種同時(shí)考慮線長(zhǎng)和擁塞的中繼器插入優(yōu)化方法,能減少插入的中繼器數(shù)量,緩解擁塞問題,并優(yōu)化互連延時(shí)。實(shí)驗(yàn)分析結(jié)果表明,相比于EDA工具自動(dòng)優(yōu)化方法,該方法將中繼器插入級(jí)數(shù)減少了8級(jí),路徑總延時(shí)減少了237ps,單元密度降低了16.7%。
[Abstract]:After the integrated circuit technology enters the nanotechnology, the interconnect has become the leading factor affecting the circuit delay. In order to ensure that the chip design can achieve the goal of timing convergence, the delay optimization of the interconnects is particularly important, in which the repeater insertion method is one of the most commonly used and most effective ways to reduce the interconnect delay. In this paper, 40 Under the nanotechnology, based on the actual engineering, the following research work is carried out on the interconnect method of the high performance microprocessor chip in the physical design of the high performance microprocessor chip. 1, the method of repeater insertion for the point to point interconnect delay. This paper is a repeater for the combination of a large number of different line lengths and different types of repeater. The results show that the time delay of the same length interconnects gradually decreases with the increase of the driver multiplier of the repeater, but the area and power consumption increase, considering the delay, power and area, the better interconnect line length is 200 m~300 mu m, and the better repeater type is 12 times the reverse phase drive. Two, optimizes the repeater insertion method of the global interconnect bus delay. This paper optimizes and estimates the repeater insertion method for the delay, crosstalk and congestion caused by a large number of global interconnection buses within the finite area between the modules, and uses the interlace insertion to optimize the position of the repeater and adopt special cloth. The line rule optimizes the parallel bus. The experimental results show that the method effectively reduces the local congestion and crosstalk, reduces the delay of the global interconnects, reduces the total delay and crosstalk of the interconnects by 25.4% and 21.8%. three respectively, and optimizes the repeater insertion method of the multi sector interconnect network delay. There are some more in physical design. The fan out interconnection network, using the EDA tool to automatically optimize the number of inserted repeater, leads to high local unit density and congestion. In this paper, a repeater insertion optimization method, which considers both the line length and congestion, can be considered to reduce the number of inserted repeater, alleviate the congestion and optimize the interconnect delay. The analysis results show that, compared with the EDA tool automatic optimization method, the method reduces the repeater insertion series by 8, the path total delay is reduced by 237ps, and the cell density is reduced by 16.7%.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN40

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本文編號(hào)：2030119