本文選題：三維集成電路 + 硅通孔��； 參考：《北京化工大學(xué)》2016年碩士論文

【摘要】：隨著集成電路技術(shù)的不斷發(fā)展,基于硅通孔(TSV, Through Silicon Vias)技術(shù)集成的三維集成電路由于具備低延遲、高集成度、低功耗等優(yōu)勢(shì)而得到廣泛的應(yīng)用。通過TSV進(jìn)行裸片間的堆疊綁定,能夠顯著減少芯片中長互連的延遲,從而提升芯片的性能。然而,由于TSV制造工藝的影響,TSV在制造和綁定過程中易于導(dǎo)致漏電等缺陷問題。如果通過使用包含缺陷的TSV對(duì)裸片進(jìn)行堆疊集成,易于導(dǎo)致最終的三維集成電路產(chǎn)品失效,從而嚴(yán)重影響三維集成電路的良率。因此,非常有必要對(duì)TSV進(jìn)行綁定前的缺陷檢測(cè),從而避免使用具有缺陷TSV的裸片進(jìn)行三維集成電路堆疊集成,達(dá)到提高三集成電路產(chǎn)品的良率并以此降低制造成本的目的。在本篇論文中,我們?cè)O(shè)計(jì)了一種TSV漏電缺陷的檢測(cè)結(jié)構(gòu),其能夠在三維集成電路綁定前對(duì)TSV進(jìn)行有效的漏電缺陷檢測(cè)。這種方法基于TSV的電容和電阻特性,將TSV的漏電電流轉(zhuǎn)化為漏電電壓的形式進(jìn)行檢測(cè)。在檢測(cè)過程中,首先對(duì)TSV進(jìn)行充電,利用可編程型檢測(cè)信號(hào)生成器將TSV在預(yù)期的時(shí)間下控制為高阻狀態(tài)。然后通過對(duì)TSV在高阻漏電后的電壓值進(jìn)行采樣,并依據(jù)采樣結(jié)果確定TSV是否存在漏電缺陷。通過仿真實(shí)驗(yàn)的結(jié)果表明,本文設(shè)計(jì)的檢測(cè)結(jié)構(gòu)功能可行,且具有較大的TSV漏電缺陷檢測(cè)范圍,且制造成本相對(duì)較低,功耗小。
[Abstract]:With the continuous development of integrated circuit technology, 3D integrated circuits based on silicon through hole TSVand through Silicon Vias technology have been widely used because of their advantages of low delay, high integration, low power consumption and so on. The stacking binding between bare chips by TSV can significantly reduce the delay of long interconnect in the chip and improve the performance of the chip. However, due to the influence of TSV manufacturing process, TSV is prone to lead to defects such as leakage during fabrication and binding. If the bare chip is stacked and integrated with TSV containing defects, it is easy to lead to the final failure of 3D integrated circuit products, thus seriously affecting the yield of 3D integrated circuit. Therefore, it is necessary to detect the defects of TSV before binding, so as to avoid the use of defective TSV bare chips for 3D integrated circuit stacking and integration, so as to improve the yield of three integrated circuit products and reduce the manufacturing cost. In this paper, we design a TSV leakage defect detection structure, which can detect TSV leakage defect effectively before 3D IC binding. Based on the capacitance and resistance characteristics of TSV, the leakage current of TSV is converted to the form of leakage voltage. In the detection process, the TSV is first charged, and the TSV is controlled to a high resistance state in the expected time by using a programmable detection signal generator. Then the voltage value of TSV after high resistance leakage is sampled, and it is determined whether TSV has leakage defect or not. The simulation results show that the structure designed in this paper is feasible and has a large detection range of TSV leakage defects, and the manufacturing cost is relatively low and the power consumption is low.
【學(xué)位授予單位】：北京化工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：TN407

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 余樂;楊海鋼;謝元祿;張甲;張春紅;韋援豐;;三維集成電路中硅通孔缺陷建模及自測(cè)試/修復(fù)方法研究[J];電子與信息學(xué)報(bào);2012年09期

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本文編號(hào)：2010712