發(fā)布時間：2018-06-03 05:05

  本文選題：LDMOS + SOI��； 參考：《杭州電子科技大學》2017年碩士論文

【摘要】：在這個快速發(fā)展的社會中,高壓集成電路被廣泛的應用在各個領域,而在高壓集成電路中,LDMOS(Laterally Diffused Metal Oxide Semiconductor)器件是該電路對高壓器件的首選之一。高壓集成電路要求在器件尺寸縮小的同時,其擊穿電壓不會降低甚至會變大。為了達到這種要求,人們主要考慮制作工藝、結(jié)構(gòu)設計和材料開發(fā)這三個方面。在本文中,為了提高LDMOS的耐壓能力,主要從器件整體結(jié)構(gòu)的設計這一方面出發(fā)考慮。由于制作在絕緣層上硅(silicon on insulator,SOI)的器件相對于制作在體硅(bulk silicon)上的器件而言,其性能上具有更多的優(yōu)點,所以本論文主要探討SOI LDMOS器件。在本文中,首先概述了SOI技術及其制備方法。然后講述了整個SOI LDMOS器件的設計方法。最后,在設計SOI LDMOS器件過程中,主要討論了柵極場板(field plate)的長度與厚度等各種參數(shù)對器件性能的影響。該論文提出了在漂移區(qū)內(nèi)有雙氧化槽結(jié)構(gòu)的SOI LDMOS器件(Double Oxide Trench SOI LDMOS),即DOT SOI LDMOS。該器件的結(jié)構(gòu)特點是在器件的漂移區(qū)上下表面各有一個氧化槽。這種結(jié)構(gòu)的優(yōu)點在于漂移區(qū)上表面的氧化槽結(jié)構(gòu)能夠改善漂移區(qū)表面的橫向電場,從而增大了器件在橫向方向上的耐壓能力;位于漂移區(qū)下表面的氧化槽結(jié)構(gòu)具有積累空穴的作用,能夠增大埋氧層上的縱向電場,從而提高LDMOS器件在縱向方向上的耐壓能力。研究結(jié)果顯示,在相同器件尺寸條件下,當DOT SOI LDMOS的溝槽寬度與厚度分別為10μm和3μm時,其擊穿電壓要比CSOI LDMOS高30.5%。本文還提出了另外一種有N/P埋層結(jié)構(gòu)的SOI LDMOS器件結(jié)構(gòu)。這種器件結(jié)構(gòu)的特點是在漂移區(qū)的右下方鋪一部分的高摻雜的N埋層或者是在漂移區(qū)的左下方鋪一部分高摻雜的P埋層。這兩種結(jié)構(gòu)均可以改善漂移區(qū)內(nèi)部的RESURF效應,使漂移區(qū)內(nèi)部的電場分布更加均勻,而且還可以使該結(jié)構(gòu)的埋氧層內(nèi)部電場變大。通過對PBPL/PBNL SOI LDMOS進行仿真與分析,結(jié)果表明:相對CSOI LDMOS而言,PBPL SOI LDMOS的擊穿電壓增加了48%,導通電阻減小了31.7%;而PBNL SOI LDMOS的耐壓能力變高了78%,導通電阻變小了13.8%。
[Abstract]:In this rapidly developing society, high voltage integrated circuits are widely used in various fields, and in high voltage integrated circuits, Laterally Diffused Metal Oxide Semiconductor) devices are the first choice for high voltage devices. High-voltage integrated circuit requires that the breakdown voltage will not decrease or even become larger while the device size is reduced. In order to achieve this requirement, people mainly consider three aspects: fabrication process, structure design and material development. In this paper, in order to improve the voltage resistance of LDMOS, the design of the whole device structure is considered. Because the devices fabricated on insulator have more advantages than those fabricated on bulk silicon, this paper mainly discusses SOI LDMOS devices. In this paper, the SOI technology and its preparation methods are first summarized. Then the design method of the whole SOI LDMOS device is described. Finally, in the process of designing SOI LDMOS device, the influence of the length and thickness of the gate field plate on the performance of the device is discussed. In this paper, double Oxide Trench SOI LDMOSs, or DOT SOI LDMOS., are proposed for SOI LDMOS devices with a double Oxide Trench SOI structure in the drift region. The structure of the device is characterized by an oxidation tank on the upper and lower surface of the drift region. The advantage of this kind of structure is that the oxidation tank structure on the surface of drift region can improve the transverse electric field on the surface of drift region, thus increasing the voltage resistance of the device in the transverse direction. The structure of the oxidation tank located on the surface of the drift region has the function of accumulating holes, which can increase the longitudinal electric field on the buried oxygen layer and improve the voltage resistance of LDMOS devices in the longitudinal direction. The results show that when the groove width and thickness of DOT SOI LDMOS are 10 渭 m and 3 渭 m respectively, the breakdown voltage is 30.5% higher than that of CSOI LDMOS under the same device size. Another SOI LDMOS device structure with N / P buried structure is also proposed in this paper. This device structure is characterized by laying a highly doped N buried layer at the lower right of the drift region or a highly doped P buried layer at the lower left side of the drift region. Both of these two structures can improve the RESURF effect in the drift region, make the electric field distribution more uniform in the drift region and increase the electric field in the buried oxygen layer of the structure. The simulation and analysis of PBPL/PBNL SOI LDMOS show that compared with CSOI LDMOS, the breakdown voltage of SOI LDMOS increases by 48 and the on-resistance decreases by 31.7, while the voltage resistance of PBNL SOI LDMOS increases by 78 and the on-resistance decreases by 13.8.
【學位授予單位】：杭州電子科技大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN386

【參考文獻】

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本文編號：1971576