發(fā)布時間：2018-05-25 03:10

  本文選題：現(xiàn)場可編程門陣列 + 布局　； 參考：《西安電子科技大學(xué)》2015年碩士論文

【摘要】：FPGA因為其開發(fā)周期短、靈活性強(qiáng)等諸多優(yōu)點,已成為當(dāng)今世界應(yīng)用最為廣泛的半導(dǎo)體器件之一。在FPGA EDA流程中,布局是非常重要的一個環(huán)節(jié),通常使用模擬退火算法來求取一個近似最優(yōu)解。但在集成電路規(guī)模日益增大的當(dāng)下,傳統(tǒng)的模擬退火算法在布局效率上越來越不能讓人滿意,而一些試圖提高布局效率的算法往往又導(dǎo)致布局質(zhì)量降低。本文以傳統(tǒng)的模擬退火算法為基礎(chǔ),提出一種改進(jìn)型的布局算法,稱為超快速退火回火算法。該算法將超快速模擬重復(fù)退火和模擬回火相結(jié)合,首先在高溫時利用超快速模擬重復(fù)退火溫度指數(shù)下降的特點,在進(jìn)行短暫的高溫隨機(jī)過程后,立刻使算法進(jìn)入到適合搜索全局最優(yōu)解的溫度,這樣就節(jié)省了大量時間,加速了算法的運(yùn)行。隨后在低溫的過程中又引入模擬回火過程,這時候溫度被當(dāng)作一個變量,在每一次溫度更新時,不僅可以下降,還可以保持不變,甚至可以上升到溫度序列的上一個溫度,這樣整個溫度序列就會被拉長,從而增加低溫階段的搜索,使得算法可以以更高的概率向全局最優(yōu)解收斂。這樣一個在高溫時加速,低溫時增加搜索次數(shù)的方式在總體上使得算法在提升布局效率的同時提高了布局的質(zhì)量。仿真實驗表明,超快速回火退火算法與傳統(tǒng)的模擬退火算法相比在布局效率方面提升11.22%,在關(guān)鍵路徑延時方面優(yōu)化1.91%,在總線長方面優(yōu)化0.16%。
[Abstract]:FPGA has become one of the most widely used semiconductor devices in the world because of its advantages of short development period and strong flexibility. Layout is a very important part of FPGA EDA process. Simulated annealing algorithm is usually used to find an approximate optimal solution. However, with the increasing scale of integrated circuits, the traditional simulated annealing algorithm is more and more unsatisfactory in layout efficiency, and some algorithms that try to improve layout efficiency often lead to poor layout quality. Based on the traditional simulated annealing algorithm, an improved layout algorithm is proposed in this paper, which is called super-fast annealing tempering algorithm. The algorithm combines ultra-fast simulated repeated annealing with simulated tempering. Firstly, at high temperature, the characteristic of decreasing temperature exponent of ultra-fast simulated repeated annealing is used, after a short period of high temperature random process, The algorithm is immediately entered into the temperature suitable for searching the global optimal solution, which saves a lot of time and speeds up the operation of the algorithm. Then a simulated tempering process is introduced in the process of low temperature, where the temperature is treated as a variable, which can not only decrease, but also remain unchanged, or even rise to the last temperature in the temperature series, each time the temperature is renewed. In this way, the whole temperature sequence will be elongated, thus increasing the search at the low temperature stage, so that the algorithm can converge to the global optimal solution with a higher probability. Such a way of accelerating at high temperature and increasing search times at low temperature makes the algorithm improve the layout efficiency while improving the quality of the layout. The simulation results show that compared with the traditional simulated annealing algorithm, the ultra-fast tempering annealing algorithm improves the layout efficiency by 11.22 points, optimizes the critical path delay by 1.91, and optimizes the bus length by 0.16.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN791;TP18

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本文編號：1931806