發(fā)布時間：2018-05-19 12:46

  本文選題：Transient + Voltage��； 參考：《湘潭大學》2015年碩士論文

【摘要】：智能電網是目前全世界節(jié)能減排的重要舉措之一,其中具有可長距離通訊的RS485網絡是智能電網中最為關鍵的通信網絡。RS485的傳輸總線一般架在室外或沿電纜鋪設,常因雷擊引發(fā)傳輸線上產生瞬變干擾而導致芯片的損壞。此外,RS485網路常采用直線拓撲結構,一條總線上掛載著數十至上百個RS485收發(fā)器,因而雷擊、浪涌產生的大電壓突變就有可能導致RS485網絡中收發(fā)芯片的同時損壞,從而導致網絡系統(tǒng)的癱瘓。所以,對電壓突變的防護是RS485芯片設計時必須考慮的問題,也是提高系統(tǒng)可靠性及安全性的關鍵所在。對于傳統(tǒng)的RS485收發(fā)器,為了達到DL/T645的標準,傳輸總線端口A、B會有人體模型(HBM,Human Body Model)15kV的規(guī)格要求,但在實際應用中,這樣的防護等級是不夠的。目前一般的解決方法是在RS485收發(fā)器總線端口處外接瞬變電壓抑制二極管(Transient Voltage Suppressor,TVS)來防止電壓突波。但一般的獨立TVS器件成本高而且使用不方便。同樣,壓敏電阻因其寄生電容大,導通電阻也高,且低電壓的壓敏電阻漏電流大,也不適合用于RS485介面保護。而利用傳統(tǒng)半導體工藝制作的TVS雖然反應速度極快,但其耐高電壓、高電流的能力不足,所以也難以抵擋雷擊浪涌的沖擊,而采用新型CMOS IC工藝,可以克服許多技術上的瓶頸。本文的主要工作是:一、通過采用CMOS工藝將TVS器件和RS485電路實現單片集成,以解決壓敏電阻寄生電容大,導通電阻高,且低電壓壓敏電阻漏電流大不適合用于RS485介面保護的弊端,同時克服傳統(tǒng)半導體制作的TVS耐高電壓、高電流的能力不足,難以抵擋雷擊浪涌的沖擊的問題。二、基于TIA/EIA的RS485通訊協(xié)議標準,采用臺灣旺宏電子股份有限公司0.5μm高壓CMOS工藝,使用Cadence Virtuoso EDA軟件設計完成一款集成有TVS器件的RS485接口芯片。芯片采用半雙工、雙向通訊方式,具有抗雷擊、浪涌、低功耗、短路保護等特點;芯片輸入阻抗為1/8單位負載,能夠并行驅動256個同類型的收發(fā)器。本文設計完成的芯片主要由接收器、驅動器以及TVS器件構成,芯片采用平衡驅動和差分接收的工作方式。芯片通過三次流片以及多次優(yōu)化和改進,實現了預先設計的指標,并順利通過了芯片廠商的性能以及可靠性等工程性測試;與國內同類產品相比,具有面積更小,抗干擾能力更強的特點。
[Abstract]:Smart grid is one of the most important measures of energy saving and emission reduction in the world at present. The RS485 network with long distance communication is the most important communication network in smart grid. RS485 transmission bus is generally built outdoors or along the cable. The chip is often damaged by transient interference on the transmission line caused by lightning strike. In addition, the RS485 network often adopts a linear topology, and dozens to hundreds of RS485 transceivers are mounted on a bus. As a result, the sudden change of large voltage caused by the surge may result in the simultaneous damage of the transceiver and transceiver chips in the RS485 network. This leads to the paralysis of the network system. Therefore, the protection of voltage mutation is an important problem in the design of RS485 chip, and also the key to improve the reliability and security of the system. For the traditional RS485 transceiver, in order to meet the standard of DL/T645, the transmission bus port AZB will have the specification requirements of the human body model RS485 / RS485 Body Model)15kV, but in practical application, this protection level is not enough. At present, the common solution is to install transient Voltage suppressor TVs at the bus port of RS485 transceiver to prevent voltage burst. But the general independent TVS device is expensive and inconvenient to use. Similarly, the varistor is not suitable for RS485 interface protection because of its large parasitic capacitance, high on-resistance and high leakage current of low-voltage varistor. Although the reaction speed of TVS made by traditional semiconductor process is very fast, its ability to withstand high voltage and high current is not enough, so it is difficult to resist the impact of lightning surge, and the new CMOS IC process can overcome many technical bottlenecks. The main work of this paper is as follows: first, the monolithic integration of TVS device and RS485 circuit is realized by using CMOS process to solve the problem of high parasitic capacitance and high on-resistance of varistor. The leakage current of low voltage varistor is not suitable for RS485 interface protection, and the problem of high voltage resistance and high current ability of TVS made by traditional semiconductor is overcome, and it is difficult to resist the impact of lightning surge. Secondly, based on the RS485 communication protocol standard of TIA/EIA, using the 0.5 渭 m high voltage CMOS process of Taiwan Wang Hong Electronics Co., Ltd., a RS485 interface chip integrated with TVS device is designed by using Cadence Virtuoso EDA software. The chip uses semi-duplex, two-way communication mode, has the characteristics of anti-lightning, surge, low power consumption, short circuit protection, etc. The input impedance of the chip is 1 / 8 unit load, and can drive 256 similar transceivers in parallel. The chip designed in this paper is composed of receiver, driver and TVS device. The chip uses balanced drive and differential reception. The chip has been optimized and improved for many times through three flow sheets, and has successfully passed the engineering tests of chip manufacturer's performance and reliability, and has a smaller area than other similar products in China. The ability of anti-interference is stronger.
【學位授予單位】：湘潭大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN402;TM76

【參考文獻】

相關碩士學位論文 前1條

1 劉錦江;CMOS電流差分緩沖放大器及電流模式濾波器的研究與設計[D];湖南大學;2012年

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本文編號：1910148