發(fā)布時間：2018-05-13 11:53

  本文選題：神經(jīng)形態(tài)芯片 + 神經(jīng)元電路　； 參考：《浙江大學》2016年碩士論文

【摘要】：近幾年來,深度學習算法快速發(fā)展,大規(guī)模的圖像處理和迭代計算對硬件提出了新的要求。傳統(tǒng)的計算機都是基于“馮諾依曼架構(gòu)”設(shè)計,即數(shù)據(jù)在處理器和內(nèi)存之間來回計算。這種架構(gòu)適合數(shù)字運算和程序執(zhí)行,但是并不適合處理圖像、聲音類信號。而人類的大腦卻可以輕松地同步處理視覺、聽覺和嗅覺等信號。通過研究人腦工作原理,學術(shù)界提出了一種不同于傳統(tǒng)計算機架構(gòu)的神經(jīng)形態(tài)芯片,在處理圖像和聲音類信號方面有重大優(yōu)勢。為此,本文提出了一種模數(shù)混合超大規(guī)模脈沖型神經(jīng)網(wǎng)絡(luò)電路。本文先介紹了生物神經(jīng)網(wǎng)絡(luò)的原理和相應(yīng)的電路模型,從理論上證明了神經(jīng)網(wǎng)絡(luò)電路設(shè)計的可行性,并根據(jù)應(yīng)用的需求和電路自身的限制定義了芯片的內(nèi)部結(jié)構(gòu)。該芯片主要分為四個模塊,神經(jīng)元電路陣列、突觸電路陣列、SRAM (Static Random Access Memory,靜態(tài)隨機存儲器)存儲單元陣列和AER (Address Event Representation)通信電路。其中,神經(jīng)元電路陣列和突觸電路陣列具有生物神經(jīng)元和突觸的時間特性,實現(xiàn)了脈沖頻率可調(diào),突觸權(quán)重可配的功能。同時,通過改變突觸電路和神經(jīng)元電路的連接關(guān)系可以實現(xiàn)多種應(yīng)用。利用AER電路,能夠讓芯片和微處理器通信,并通過更新SRAM單元中的突觸權(quán)重值來研究不同種類的STDP (Spike-Timing Dependent Plasticity)學習算法的效果。該芯片采用了smic 180nm CMOS工藝,包含了總共32×32個SRAM單元,2×32個突觸電路,32個IF神經(jīng)元電路和AER通信電路。仿真結(jié)果顯示,該芯片的輸出和軟件算法的輸出完全相同,表明設(shè)計的芯片符合預(yù)期的要求。
[Abstract]:In recent years, deep learning algorithms have developed rapidly. Large scale image processing and iterative computing have put forward new requirements for hardware. Traditional computers are based on "Von Neumann architecture", that is, the data is calculated back and forth between the processor and the memory. This architecture is suitable for digital computing and program execution, but it is not suitable for processing graphs. Like, sound like signals. The human brain can easily synchronize the signals of vision, hearing and smell. By studying the working principle of the human brain, the academic community has proposed a neural morphologic chip different from the traditional computer architecture, which has a great advantage in the processing of images and sound signals. For this reason, a kind of ADM is proposed. In this paper, the principle of the neural network and the corresponding circuit model are introduced. The feasibility of the design of the neural network is proved theoretically, and the internal structure of the chip is defined according to the requirements of the application and the limitation of the circuit itself. The chip is divided into four modules, the neuron circuit is divided into two modules. Array, synapse circuit array, SRAM (Static Random Access Memory, static random memory) storage unit array and AER (Address Event Representation) communication circuit. In which, the neuron circuit array and the synaptic circuit array have the time characteristics of the biological neuron and synapse, realizing the pulse frequency adjustable, the synaptic weight can match work. At the same time, a variety of applications can be realized by changing the connection between the synaptic circuit and the neuron circuit. Using the AER circuit, the chip and the microprocessor can communicate, and the effect of the different kinds of STDP (Spike-Timing Dependent Plasticity) learning algorithm is studied by updating the synaptic weight value in the SRAM unit. The chip uses SMI The C 180nm CMOS process includes a total of 32 x 32 SRAM units, 2 x 32 synaptic circuits, 32 IF neuron circuits and AER communication circuits. The simulation results show that the output of the chip is exactly the same as the output of the software algorithm, indicating that the designed chip meets the expected requirements.

【學位授予單位】：浙江大學
【學位級別】：碩士
【學位授予年份】：2016
【分類號】：TN402

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本文編號：1883032