本文選題：協(xié)同仿真 + IP核驗(yàn)證��； 參考：《哈爾濱工業(yè)大學(xué)》2015年碩士論文

【摘要】：伴隨著So C芯片設(shè)計(jì)規(guī)模的不斷提升,驗(yàn)證成本的不斷增加,軟硬件協(xié)同仿真技術(shù)以及基于平臺(tái)的So C驗(yàn)證思想已成為業(yè)界主流。同時(shí),隨著FPGA設(shè)計(jì)的逐漸完善,基于FPGA的協(xié)同仿真不僅具有高效性更具有真實(shí)性,在提升整體驗(yàn)證效果方面,該研究具有重要意義。本文基于協(xié)同仿真思想,采用千兆以太網(wǎng)作為通信媒介,結(jié)合Leon3 So C平臺(tái)與Xilinx公司的So PC系統(tǒng)構(gòu)建了一個(gè)新型的IP核驗(yàn)證平臺(tái)。該平臺(tái)主要分為PC端與FPGA端兩部分,PC端作為整個(gè)驗(yàn)證平臺(tái)的主體,包含了四個(gè)并行運(yùn)行的進(jìn)程——Leon3 So C進(jìn)程、TCP服務(wù)器進(jìn)程、驗(yàn)證功能進(jìn)程以及拓展功能進(jìn)程,進(jìn)程間的數(shù)據(jù)通信采用文本文件以及共享內(nèi)存兩種方式,同步控制信號(hào)采用了Event模式進(jìn)行通信;FPGA端主要分為硬件邏輯部分以及So PC軟件部分,在硬件邏輯中包含待測(cè)IP核。兩者之間的通信采用了TCP協(xié)議進(jìn)行可靠傳輸,在PC端采用Winsock API,在So PC軟件中使用lwip庫(kù)。同時(shí)為了便于IP核驗(yàn)證的進(jìn)行,本文提出了一種基于以太網(wǎng)的自定義數(shù)據(jù)幀,與TCP協(xié)議聯(lián)合使用。在本文最后給出了基本功能驗(yàn)證、基本性能測(cè)試以及基于Leon3 So C平臺(tái)的整體功能驗(yàn)證的具體結(jié)果。實(shí)驗(yàn)表明,該IP核驗(yàn)證平臺(tái)基本功能與整體功能均可以正常運(yùn)行,并且在待測(cè)IP核邏輯較為復(fù)雜時(shí)(如達(dá)到1024位乘法器或以上復(fù)雜度),在驗(yàn)證速度方面具有較大優(yōu)勢(shì)。
[Abstract]:With the increasing scale of so C chip design and the increasing cost of verification, hardware / software co-simulation technology and platform based so C verification idea have become the mainstream of the industry. At the same time, with the gradual improvement of FPGA design, the collaborative simulation based on FPGA not only has high efficiency and authenticity, but also plays an important role in improving the overall verification effect. In this paper, based on the cooperative simulation idea, a new IP core verification platform is constructed by using Gigabit Ethernet as the communication medium and combining the Leon3 so C platform with Xilinx's so PC system. The platform is divided into two parts: PC and FPGA as the main part of the whole verification platform, which includes four parallel running processes: Leon3 so C process, FPGA server process, verification function process and extended function process. The data communication between processes adopts two ways: text file and shared memory. The synchronous control signal uses Event mode to communicate. The FPGA end is mainly divided into hardware logic part and so PC software part, which includes IP core to be tested in the hardware logic. The communication between them adopts TCP protocol for reliable transmission, Winsock API for PC end and lwip library for so PC software. At the same time, in order to facilitate IP core verification, this paper proposes a custom data frame based on Ethernet, which is used in conjunction with TCP protocol. At the end of this paper, the results of basic function verification, basic performance test and the whole function verification based on Leon3 so C platform are given. Experiments show that both the basic function and the whole function of the IP core verification platform can run normally, and that the verification speed of the IP core verification platform can be greatly improved when the logic of the IP core under test is more complex (such as 1024 bit multiplier or more complexity).
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN47

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本文編號(hào)：1882800