本文選題：∑ + -ΔADC��； 參考：《遼寧大學(xué)》2015年碩士論文

【摘要】：???ADC主要通過過采樣技術(shù)、噪聲整形技術(shù)、反饋以及數(shù)字濾波技術(shù)的運(yùn)用,來達(dá)到提高信噪比與性能的目的,完成了模擬信號到數(shù)字信號的高精度轉(zhuǎn)換。它廣泛應(yīng)用于音頻領(lǐng)域。本文完成了一種適用于音頻的16 bit???ADC調(diào)制器的設(shè)計(jì)。首先,分析與研究了???ADC的原理,通過對???調(diào)制器各種結(jié)構(gòu)的對比,根據(jù)設(shè)計(jì)要求,選定2-1MASH結(jié)構(gòu)作為本文設(shè)計(jì)???調(diào)制器的結(jié)構(gòu)。其次,對量化器位數(shù)、過采樣率加以確定,選擇1位量化器,過采樣率為128倍,借助Matlab對系統(tǒng)進(jìn)行建模仿真。再次,討論了???調(diào)制器的各項(xiàng)非理想因素,在Matlab Simulink中對其仿真,為放大器的設(shè)計(jì)提出了性能指標(biāo)。最后,在系統(tǒng)設(shè)計(jì)的基礎(chǔ)之上,對???調(diào)制器的各個模塊部分進(jìn)行了電路設(shè)計(jì),并利用Cadence Spectre加以仿真驗(yàn)證。論文在???調(diào)制器設(shè)計(jì)方面的探索主要包括:(1)使用Matlab對系統(tǒng)建模,優(yōu)化了系統(tǒng)參數(shù),實(shí)現(xiàn)了一個優(yōu)化的系統(tǒng)結(jié)構(gòu);(2)通過系統(tǒng)級對非理想因素的分析,確定了運(yùn)放的性能指標(biāo),并以之指導(dǎo)、優(yōu)化電路結(jié)構(gòu)的設(shè)計(jì);(3)采用了一種低功耗、高速的鎖存比較器,提高了電路的性能。本文設(shè)計(jì)的???調(diào)制器基于Chrt 0.35μm標(biāo)準(zhǔn)CMOS工藝,信號帶寬為20 KHz,過采樣率128,采樣信號頻率5.12 MHz。通過仿真驗(yàn)證表明,本文設(shè)計(jì)的???調(diào)制器SNDR為95.2 d B,有效位數(shù)為15.51 bit,滿足設(shè)計(jì)要求。
[Abstract]:Through the application of over-sampling, noise shaping, feedback and digital filtering, ADC achieves the purpose of improving signal-to-noise ratio (SNR) and performance, and completes the high-precision conversion from analog signal to digital signal. It is widely used in audio field. In this paper, a 16 bit???ADC modulator for audio frequency is designed. Firstly, the principle of ADC is analyzed and studied. According to the design requirements, the 2-1MASH structure is selected as the design design of the modulator. The structure of the modulator. Secondly, the quantizer bit number and over-sampling rate are determined, and one quantizer is selected. The over-sampling rate is 128-fold. The system is modeled and simulated by Matlab. Again, discussed? The non-ideal factors of the modulator are simulated in Matlab Simulink, and the performance index is proposed for the design of the amplifier. Finally, on the basis of the design of the system, Each module of modulator is designed and simulated by Cadence Spectre. Is the paper in? The exploration of modulator design mainly includes: using Matlab to model the system, optimizing the system parameters and realizing an optimized system structure. Through the analysis of the non-ideal factors at the system level, the performance index of the operational amplifier is determined and guided. A low power and high speed latch comparator is used to improve the performance of the circuit. The design of this paper? The modulator is based on Chrt 0.35 渭 m standard CMOS technology, the signal bandwidth is 20 kHz, the over-sampling rate is 128, and the sampling frequency is 5.12 MHz. The simulation results show that the design of this paper is very important. The modulator SNDR is 95.2 dB and the effective bit is 15.51 bit, which meets the design requirements.
【學(xué)位授予單位】：遼寧大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN761

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本文編號：1849654