本文選題：高速 + 高密度　； 參考：《西南交通大學(xué)》2015年碩士論文

【摘要】：高速高密度電路板是現(xiàn)階段電子系統(tǒng)發(fā)展的必然趨勢(shì),在強(qiáng)輻射源與高功率微波領(lǐng)域中,由高速和高密度環(huán)境引起的信號(hào)完整性和電源完整性問(wèn)題不容忽視。本文針對(duì)某基于FPGA電機(jī)控制系統(tǒng)的高速高密度電路板,分析其板級(jí)信號(hào)完整性和電源完整性問(wèn)題,以及連接器的信號(hào)完整性問(wèn)題。本文對(duì)高速高密度PCB信號(hào)完整性和電源完整性進(jìn)行研究。首先,明確高速、高密度、信號(hào)完整性和電源完整性的基本概念,調(diào)研國(guó)內(nèi)外信號(hào)完整性和電源完整性的研究現(xiàn)狀,分析其產(chǎn)生原因和表現(xiàn)形式,如串?dāng)_、反射和同步開(kāi)關(guān)噪聲等,并對(duì)這些表現(xiàn)形式進(jìn)行深入研究,分析其產(chǎn)生的根本原因、影響因素和減小不良影響的方法。其次,對(duì)該P(yáng)CB進(jìn)行層疊結(jié)構(gòu)的分析和設(shè)計(jì),通過(guò)傳輸線類(lèi)型的分析和特性阻抗的計(jì)算得到不同信號(hào)層傳輸線的線寬及厚度,預(yù)估計(jì)串?dāng)_影響,根據(jù)3W原則、3H原則和布線需求得到線距,完成布局和布線的設(shè)計(jì)。利用FPGA的可編程性建立高低速混合模型,根據(jù)電機(jī)控制信號(hào)線和SDRAM信號(hào)線時(shí)序要求的不同,選擇恰當(dāng)?shù)腎BIS驅(qū)動(dòng)器模型,建立時(shí)域電路模型進(jìn)行時(shí)域仿真,得到傳輸線的傳輸特性,并選擇多跟相鄰傳輸線進(jìn)行串?dāng)_分析。然后,對(duì)FPGA負(fù)載進(jìn)行最優(yōu)化設(shè)計(jì),通過(guò)仿真計(jì)算Z-f曲線和電源紋波,分析兩種不同負(fù)載方案的優(yōu)劣并確定負(fù)載方案。根據(jù)Z-f曲線設(shè)計(jì)去耦網(wǎng)絡(luò),添加去耦電容,降低目標(biāo)阻抗以減小電源紋波。在完成優(yōu)化負(fù)載和去耦網(wǎng)絡(luò)設(shè)計(jì)的基礎(chǔ)上,從理論分析和仿真驗(yàn)證的角度,分析過(guò)孔結(jié)構(gòu)對(duì)電源分配網(wǎng)絡(luò)性能的影響,得到過(guò)孔內(nèi)徑、焊盤(pán)和反焊盤(pán)的最佳設(shè)計(jì)尺寸,指出除了傳統(tǒng)的優(yōu)化負(fù)載設(shè)計(jì)和添加去耦電容的方式之外,還可以通過(guò)修改過(guò)孔結(jié)構(gòu)優(yōu)化電源紋波,實(shí)現(xiàn)電源紋波的最優(yōu)化設(shè)計(jì)。對(duì)電機(jī)控制板與電機(jī)之間某型號(hào)連接器進(jìn)行仿真分析。運(yùn)用仿真軟件對(duì)其3D建模,運(yùn)用場(chǎng)路結(jié)合的分析方法,計(jì)算其S參數(shù),提取并導(dǎo)入時(shí)域仿真軟件,得到連接器的傳輸特性。取相鄰的多對(duì)引腳進(jìn)行分析,仿真計(jì)算其串?dāng)_影響。對(duì)比傳統(tǒng)的阻抗匹配方式進(jìn)行優(yōu)化,指出阻抗匹配法的局限性；采用從高速到低速轉(zhuǎn)換的方法,完成連接器傳輸特性的優(yōu)化,使連接器在PCB中得以良好的運(yùn)用。根據(jù)前文仿真內(nèi)容完成PCB的設(shè)計(jì)并加工,得到實(shí)物。用示波器對(duì)加工完成的PCB進(jìn)行測(cè)試分析,得到單根傳輸線的傳輸特性,對(duì)比仿真結(jié)果,驗(yàn)證PCB傳輸線具有良好的傳輸特性。測(cè)試電容引腳兩端電源紋波,驗(yàn)證PCB的電源紋波滿足應(yīng)用需求,具有較好的電源完整性。
[Abstract]:High speed and high density circuit board is the inevitable trend of electronic system development at present. In the field of strong emitter and high power microwave, the signal integrity and power integrity caused by high speed and high density environment can not be ignored.In this paper, the problems of board level signal integrity, power supply integrity and connector signal integrity are analyzed for a high speed and high density circuit board based on FPGA motor control system.In this paper, the signal integrity and power integrity of high speed and high density PCB are studied.First of all, make clear the basic concepts of high speed, high density, signal integrity and power integrity, investigate the research status of signal integrity and power integrity at home and abroad, analyze their causes and manifestations, such as crosstalk,The reflection and synchronous switching noise and so on are studied in depth to analyze the root causes of these manifestations, the influencing factors and the methods to reduce the adverse effects.Secondly, the stack structure of the PCB is analyzed and designed. Through the analysis of transmission line type and the calculation of characteristic impedance, the line width and thickness of different signal layer transmission lines are obtained, and the influence of crosstalk is pre-estimated.According to the 3W principle and the routing requirement, the distance between the lines is obtained, and the layout and routing design is completed.The high and low speed hybrid model is established by using the programmability of FPGA. According to the different timing requirements of the motor control signal line and the SDRAM signal line, the appropriate IBIS driver model is selected, and the time domain circuit model is established to carry out the time domain simulation.The transmission characteristics of transmission lines are obtained, and crosstalk analysis of multiple adjacent transmission lines is carried out.Then, the optimal design of FPGA load is carried out. The Z-f curve and the power ripple are simulated and calculated. The advantages and disadvantages of the two different load schemes are analyzed and the load schemes are determined.According to Z-f curve, decoupling network is designed, decoupling capacitance is added, and target impedance is reduced to reduce the ripple of power supply.On the basis of the optimization of load and decoupling network design, from the angle of theoretical analysis and simulation verification, this paper analyzes the influence of the perforated structure on the performance of the power distribution network, and obtains the optimum design size of the overhole inner diameter, the pad and the reverse pad.It is pointed out that in addition to the traditional ways of optimizing load design and adding decoupling capacitors, the optimal design of power ripple can also be realized by modifying the structure of perforated power supply.A certain type of connector between motor control board and motor is simulated and analyzed.The 3D model was modeled by simulation software, and the S parameters were calculated by the method of field circuit analysis. The time domain simulation software was extracted and imported, and the transmission characteristics of the connector were obtained.Several pairs of adjacent pins are analyzed and the crosstalk effect is simulated.Compared with the traditional impedance matching method, the limitation of the impedance matching method is pointed out, and the transmission characteristics of the connector are optimized by using the method of high speed to low speed conversion, so that the connector can be well used in PCB.According to the above simulation content, the design and processing of PCB are completed, and the object is obtained.The transmission characteristics of a single transmission line are obtained by testing and analyzing the finished PCB by oscilloscope. The simulation results show that the PCB transmission line has good transmission characteristics.The power ripple at both ends of the capacitor pin is tested to verify that the power ripple of PCB meets the requirement of application and has good power integrity.
【學(xué)位授予單位】：西南交通大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN41

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本文編號(hào)：1773834