本文選題：硅通孔(TSV) + 低溫電感耦合等離子體增強型化學氣相淀積(ICPECVD)��； 參考：《半導體技術(shù)》2017年08期

【摘要】：提出了一種基于硅通孔(TSV)和激光刻蝕輔助互連的改進型CMOS圖像傳感器(CIS)圓片級封裝方法。對CIS芯片電極背部引出的關(guān)鍵工藝,如錐形TSV形成、TSV絕緣隔離、重布線(RDL)等進行了研究。采用低溫電感耦合等離子體增強型化學氣相淀積(ICPECVD)的方法實現(xiàn)TSV內(nèi)絕緣隔離;采用激光刻蝕開口和RDL方法實現(xiàn)CIS電極的背部引出;通過采用鋁電極電鍍鎳層的方法解決了激光刻蝕工藝中聚合物溢出影響互連的問題,提高了互連可靠性。對錐形TSV刻蝕參數(shù)進行了優(yōu)化。最終在4英寸(1英寸=2.54 cm)硅/玻璃鍵合圓片上實現(xiàn)了含有276個電極的CIS圓片級封裝。電性能測試結(jié)果表明,CIS圓片級封裝具有良好的互連導電性,兩個相鄰電極間平均電阻值約為7.6Ω。
[Abstract]:A wafer level packaging method for an improved CMOS image sensor based on silicon through hole (TSVV) and laser etching assisted interconnection is proposed in this paper.The key technology of back extraction of CIS chip electrode, such as tapered TSV to form insulation isolation, rewiring, etc., has been studied in this paper.The low temperature inductively coupled plasma enhanced chemical vapor deposition (ICP-ECVD) method is used to isolate the internal insulation of TSV, the laser etching opening and the RDL method are used to realize the back extraction of the CIS electrode.By means of electroplating nickel layer with aluminum electrode, the problem of polymer spillover affecting interconnection in laser etching process is solved, and the interconnect reliability is improved.The etching parameters of conical TSV were optimized.Finally, CIS wafer packaging with 276 electrodes was realized on 4 inch / 1 inch / 2.54 cm) silicon / glass bonded wafer.The electrical performance test results show that the CIS wafer packaging has good interconnection conductivity, and the average resistance between the two adjacent electrodes is about 7.6 惟.
【作者單位】： 上海大學索朗光伏材料與器件R&D聯(lián)合實驗室;中國科學院上海微系統(tǒng)與信息技術(shù)研究所傳感技術(shù)聯(lián)合國家重點實驗室;
【基金】：國家自然科學基金資助項目(61574154) 上海市自然科學基金資助項目(13ZR1447300)
【分類號】：TN405;TP212

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本文編號：1767783