本文選題：802.11i標準　切入點：CCMP協(xié)議　出處：《華中科技大學》2015年碩士論文

【摘要】：隨著無線網絡的普及應用,其安全性面臨巨大的挑戰(zhàn),802.11b標準定義的WEP安全協(xié)議無法抵御密鑰恢復攻擊,因此2004年IEEE無線標準小組公布了802.11i安全補充標準,其關鍵在于提出了安全高效的CCMP加密協(xié)議。隨著無線網絡速度的提升,基于軟件和傳統(tǒng)硬件實現(xiàn)協(xié)議難以滿足系統(tǒng)吞吐率的需求,因此需要采用并行高效的FPGA硬件平臺實現(xiàn)CCMP安全協(xié)議。本文在深入研究CCMP協(xié)議工作機制及其核心加密算法AES的基礎上,以高吞吐率為目標,設計了基于FPGA的硬件系統(tǒng)。首先進行架構設計將系統(tǒng)劃分為高性能AES模塊、AES_CCM模塊、格式化模塊、主控模塊等四個主要部分。然后進行子模塊設計,在實現(xiàn)AES模塊時采取輪融合技術,進而縮減周期數,提高數據吞吐率;在實現(xiàn)AES_CCM模塊時,采用雙AES核技術,確保AES_CBC_MAC模塊和AES_CTR模塊并行執(zhí)行,提高運算效率;在格式化模塊中,設計了數據緩沖結構,使本系統(tǒng)具備更好的兼容性,以便處理不同速率的數據流;在主控模塊及子模塊的控制流設計過程中,采取優(yōu)化控制信號等方法,降低關鍵路徑延遲。最后在合理設計架構并提高子模塊運算效率的基礎上,實現(xiàn)基于FPGA的高吞吐率CCMP協(xié)議硬件系統(tǒng)設計。基于Modelsim仿真軟件和集成邏輯分析儀對CCMP硬件系統(tǒng)進行仿真驗證。然后在Xilinx Vivado開發(fā)環(huán)境中,以Virtex-7為目標FPGA,進行綜合實現(xiàn)以及時序分析,得出系統(tǒng)最高數據吞吐率可達2.185 Gbps。通過與傳統(tǒng)設計的全面性能比較,結果表明本文提出的設計方案較為合理,在系統(tǒng)吞吐率、資源利用率等方面均有所提升。
[Abstract]:With the popularization and application of wireless network, the security of WEP protocol defined by 802.11b standard cannot resist the attack of key recovery. So in 2004, the 802.11i security supplement standard was published by the IEEE Wireless Standards Group.The key is to propose a secure and efficient CCMP encryption protocol.With the improvement of wireless network speed, it is difficult to meet the requirements of system throughput based on software and traditional hardware implementation protocols, so it is necessary to use parallel and efficient FPGA hardware platform to implement CCMP security protocol.On the basis of deeply studying the working mechanism of CCMP protocol and its core encryption algorithm AES, this paper designs a hardware system based on FPGA aiming at high throughput.Firstly, the system is divided into four main parts: AESCCM module, format module and main control module.Then the sub-module is designed, the wheel fusion technology is adopted in the realization of AES module, and the cycle number is reduced, and the data throughput is improved. When the AES_CCM module is implemented, the dual AES kernel is adopted to ensure the parallel execution of AES_CBC_MAC module and AES_CTR module.In the format module, the data buffer structure is designed to make the system have better compatibility, in order to deal with the data flow of different rates; in the process of the control flow design of the main control module and sub-module,The critical path delay is reduced by optimizing the control signal.Finally, on the basis of reasonably designing the architecture and improving the operation efficiency of sub-modules, the hardware system design of CCMP protocol with high throughput based on FPGA is realized.Based on Modelsim simulation software and integrated logic analyzer, the CCMP hardware system is simulated and verified.Then in the Xilinx Vivado development environment, taking Virtex-7 as the target, the system is implemented synthetically and the timing is analyzed. It is concluded that the maximum data throughput of the system can reach 2.185 Gbps.Compared with the traditional design, the results show that the design scheme proposed in this paper is reasonable, and the system throughput and resource utilization are improved.
【學位授予單位】：華中科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN791;TN915.04

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本文編號：1709150