本文選題：老化　切入點(diǎn)：ATPG　出處：《合肥工業(yè)大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著當(dāng)前集成電路特征尺寸不斷減小,在帶來頻率功耗等性能的提升的同時(shí),一些嚴(yán)重的電路可靠性問題也逐漸顯現(xiàn)。其中負(fù)偏置溫度不穩(wěn)定性(Negative Bias Temperature Instability, NBTI)因?yàn)闀?huì)顯著導(dǎo)致PMOS的柵極閾值電壓上升,被認(rèn)為是產(chǎn)生電路老化現(xiàn)象的主要物理效應(yīng)之一。在最為極端的模型中,在10年內(nèi)由NBTI效應(yīng)導(dǎo)致的電路時(shí)延增長量預(yù)測值最大為20%。通過減輕NBTI,可以有效緩解集成電路的老化效應(yīng),提高集成電路的可靠性。邏輯門的輸入狀態(tài)會(huì)對(duì)電路的老化效應(yīng)產(chǎn)生直接影響,因而集成電路待機(jī)模式下的輸入矢量也會(huì)對(duì)電路的老化狀態(tài)有很大影響,本文由此提出一種基于門故障插入的輸入矢量控制方法。首先,根據(jù)邏輯門所經(jīng)過的關(guān)鍵路徑數(shù)量的不同,在整個(gè)電路中先提取出對(duì)老化效應(yīng)影響較大的關(guān)鍵邏輯門,避免了對(duì)整個(gè)電路進(jìn)行抗老化防護(hù)帶來的過大的額外面積和功耗開銷。在提取的關(guān)鍵門集合中,插入根據(jù)一定規(guī)則放置的固定故障,最終由這些固定故障生成的輸入矢量可以使得相應(yīng)邏輯門電路處于老化恢復(fù)狀態(tài)。同時(shí)在插入固定故障時(shí)考慮了晶體管的堆疊效應(yīng),大大減少了實(shí)際需要插入的故障數(shù)量,仿真數(shù)據(jù)顯示在不同測試電路中的插入故障數(shù)均減少到之前的50%以上。得到完整的插入故障列表后,通過自動(dòng)向量生成工具(Automatic Test Pattern Generation, ATPG)生成的初步的抗老化輸入矢量集合。對(duì)這些輸入矢量集合進(jìn)行進(jìn)一步的篩選以得到最優(yōu)輸入矢量�；陂T故障的抗老化輸入矢量控制方法對(duì)于不同的電路需要進(jìn)行各自相應(yīng)的計(jì)算,得到不同的輸入矢量,因此需要加入專門輸入控制電路以實(shí)現(xiàn)該抗老化方法,本文在板級(jí)和芯片級(jí)分別設(shè)計(jì)了硬件實(shí)現(xiàn)電路,可以在電路的待機(jī)模式下自動(dòng)加載相應(yīng)的抗老化輸入矢量,同時(shí)在活動(dòng)模式下不對(duì)輸入端口的正�；顒�(dòng)造成干擾。為測試產(chǎn)生的抗老化輸入矢量對(duì)電路的防護(hù)效果,本文提出了一種基于C++程序的測試電路建模和靜態(tài)時(shí)序分析方法。通過讀取測試電路的網(wǎng)表文件,建立電路的邏輯門級(jí)的時(shí)延模型,并通過深度優(yōu)先遍歷和路徑拓?fù)渑判虻姆椒▽㈦娐分兴写嬖诼窂教崛〕?從而在電路的不同路徑上應(yīng)用NBTI模型進(jìn)行老化時(shí)延的計(jì)算。在對(duì)ISCAS85測試電路的實(shí)驗(yàn)中表明該方法相較于隨機(jī)輸入矢量方法有17%的時(shí)延改善量。
[Abstract]:With the decreasing of the feature size of the current integrated circuit, the frequency power consumption and other performance are improved, at the same time, Some serious circuit reliability problems are emerging, including negative bias temperature instability and negative Bias Temperature stability (NBTI), which can significantly increase the gate threshold voltage of PMOS. Is considered to be one of the main physical effects of circuit aging. In the most extreme models, The predicted value of delay growth caused by NBTI effect in 10 years is 20. By mitigating NBTIs, the aging effect of integrated circuits can be effectively alleviated. To improve the reliability of integrated circuits, the input state of logic gates will have a direct impact on the aging effect of circuits, so the input vectors in standby mode of integrated circuits will also have a great impact on the aging state of circuits. In this paper, an input vector control method based on gate fault insertion is proposed. Firstly, according to the number of critical paths passed by logic gates, the key logic gates which have a great influence on aging effect are first extracted in the whole circuit. The extra area and power cost caused by anti-aging protection of the whole circuit are avoided. In the extracted key gate set, a fixed fault is inserted according to certain rules. Finally, the input vectors generated by these fixed faults can make the corresponding logic gates in the aging recovery state. At the same time, the stacking effect of transistors is taken into account in the insertion of fixed faults, which greatly reduces the number of actual faults that need to be inserted. Simulation data show that the number of insert faults in different test circuits is reduced to more than 50% of the previous ones. The initial set of anti-aging input vectors generated by automatic Test Pattern Generation (ATPGs) is used to obtain the optimal input vectors by further screening these sets of input vectors. The anti-aging input vectors based on gate faults are obtained. For different circuits, the quantity control method needs to do their own calculation. Different input vectors are obtained, so it is necessary to add special input control circuit to realize the anti-aging method. In this paper, the hardware implementation circuit is designed at the board level and the chip level, respectively. The anti-aging input vector can be automatically loaded in the standby mode of the circuit, and the normal activity of the input port can not be interfered with in the active mode. In this paper, a method of modeling and static timing analysis of test circuit based on C program is proposed. By reading the network table file of the test circuit, the logic gate delay model of the circuit is established. Furthermore, all existing paths in the circuit are extracted by depth-first traversal and path topology sorting. The NBTI model is used to calculate the aging delay in different paths of the circuit. The experimental results of the ISCAS85 test circuit show that the proposed method can improve the delay by 17% compared with the random input vector method.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN40

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本文編號(hào)：1648040