本文選題：FPGA　切入點(diǎn)：Verilog　出處：《蘭州交通大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著以太網(wǎng)通信技術(shù)的不斷發(fā)展,人們對網(wǎng)絡(luò)通信的速度及安全傳輸要求越來越高,以太網(wǎng)通信技術(shù)應(yīng)用越來越廣泛。但由于以太網(wǎng)協(xié)議的復(fù)雜性,實際應(yīng)用中系統(tǒng)處理無法更好地滿足實時性的需求。FPGA等可編程邏輯器件的快速發(fā)展使得以太網(wǎng)傳輸實時性更高,隨著硬件以太網(wǎng)協(xié)議棧技術(shù)水平越來越高,如今基于FPGA的以太網(wǎng)協(xié)議處理變?yōu)橐粋�研究熱點(diǎn)。本文在FPGA平臺上,用Candence軟件及Verilog HDL語言設(shè)計并實現(xiàn)了一個高效的基于FPGA和W5500通過以太網(wǎng)服務(wù)器控制的串口數(shù)據(jù)切換系統(tǒng),運(yùn)用FPGA對串口協(xié)議轉(zhuǎn)換電路中的TCP/IP協(xié)議棧進(jìn)行初始化并進(jìn)行相應(yīng)的通道切換,提高系統(tǒng)的可復(fù)用性,為更深層次的研究提供更加便利的平臺。硬件部分主要包括電平轉(zhuǎn)換電路、通道切換電路、以太網(wǎng)協(xié)議轉(zhuǎn)換電路、網(wǎng)口傳輸電路以及系統(tǒng)供電電路五個部分,為協(xié)議轉(zhuǎn)換提供一種可添加、可用多種電平轉(zhuǎn)換的思路,只要符合該電平傳輸就能方便地加入到協(xié)議轉(zhuǎn)換電路中進(jìn)行運(yùn)行和調(diào)試。協(xié)議轉(zhuǎn)換電路負(fù)責(zé)主要的算法實現(xiàn),通過硬件形式實現(xiàn)整個設(shè)計。全硬件的TCP/IP協(xié)議棧協(xié)議傳輸,可使傳輸效率最大化,實現(xiàn)數(shù)據(jù)透明傳輸。軟件部分主要包括TCP/IP協(xié)議棧初始化及鏈路切換兩個部分。實現(xiàn)服務(wù)器與FPGA控制下的TCP/IP協(xié)議棧之間的以太網(wǎng)通信設(shè)計,如TCP/IP、UDP算法設(shè)計、嵌入式以太網(wǎng)芯片初始化及串口通路切換程序?qū)崿F(xiàn)等。整個設(shè)計在Candence和Quartus II 13.0以及ISE 14.7的軟件環(huán)境下開發(fā),在自主設(shè)計的硬件平臺上實現(xiàn),在軟件仿真過程采用ISE 14.7的Qsim和Modelsim做為輔助分析軟件。通過對仿真實驗結(jié)果分析及硬件電路調(diào)試等,可以驗證本設(shè)計在硬件方面和軟件方面的功能都達(dá)到了預(yù)期要求。
[Abstract]:With the continuous development of Ethernet communication technology, people have higher and higher requirements for the speed and secure transmission of network communication, Ethernet communication technology is more and more widely used, but due to the complexity of Ethernet protocol, The rapid development of programmable logic devices such as FPGA can not better meet the requirement of real-time performance in practical applications, which makes Ethernet transmission more real-time. With the increasing level of hardware Ethernet protocol stack technology, Nowadays, Ethernet protocol processing based on FPGA has become a research hotspot. In this paper, an efficient serial port data switching system based on FPGA and W5500 is designed and implemented on FPGA platform with Candence software and Verilog HDL language. The FPGA is used to initialize the TCP/IP protocol stack in the serial port protocol conversion circuit and the corresponding channel switch is carried out to improve the reusability of the system and provide a more convenient platform for further research. The hardware part mainly includes the level conversion circuit. Channel switching circuit, Ethernet protocol conversion circuit, network port transmission circuit and system power supply circuit provide a kind of idea that can be added for protocol conversion and can be used for multi-level conversion. So long as it conforms to this level transmission, it can be easily added to the protocol conversion circuit to run and debug. The protocol conversion circuit is responsible for the main algorithm realization, and the whole design is realized through the hardware form, and the whole hardware TCP/IP protocol stack protocol transmission is realized. The software mainly includes two parts: initialization of TCP/IP protocol stack and link switching. The Ethernet communication between server and TCP/IP protocol stack under FPGA control is realized, such as TCP / IP / UDP algorithm design. The embedded Ethernet chip initialization and serial port path switch program are realized. The whole design is developed under the software environment of Candence, Quartus II 13.0 and ISE 14.7, and realized on the hardware platform of independent design. In the software simulation process, Qsim and Modelsim of ISE 14.7 are used as the assistant analysis software. Through the analysis of the simulation results and the debugging of the hardware circuit, it can be verified that the functions of the design in the hardware and software are up to the expected requirements.
【學(xué)位授予單位】：蘭州交通大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TP393.11;TN791

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