本文選題：PCI　切入點(diǎn)：仲裁　出處：《西安電子科技大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著集成電路的不斷發(fā)展,產(chǎn)品功能的多樣性和系統(tǒng)的復(fù)雜性,使得設(shè)計(jì)驗(yàn)證必須更加嚴(yán)謹(jǐn),我們必須更加努力的去保證設(shè)計(jì)的正確性。我們需要選擇合適的驗(yàn)證方法和高效的驗(yàn)證平臺(tái),才能提高對(duì)復(fù)雜芯片驗(yàn)證的效率。PCI總線,是系統(tǒng)中常用的總線之一,從低端的移動(dòng)領(lǐng)域到高端的處理器,我們都可以找到它的應(yīng)用。為了滿足應(yīng)用要求,系統(tǒng)結(jié)構(gòu)越來越復(fù)雜。但是,單一的PCI總線上,負(fù)載的設(shè)備數(shù)目是有限的。為了實(shí)現(xiàn)總線的擴(kuò)展,通常使用橋設(shè)備,來形成分級(jí)的總線結(jié)構(gòu)。為了能夠支持這種復(fù)雜的總線結(jié)構(gòu),提高總線使用的效率,我們需要一種靈活的仲裁方法,來分配總線的使用權(quán)。驗(yàn)證工作,在當(dāng)代集成電路設(shè)計(jì)中所占的時(shí)間和資源都遠(yuǎn)大于設(shè)計(jì)工作。所以本文主要的工作量也集中在驗(yàn)證部分。在建立驗(yàn)證方案后,最重要的工作就是搭建驗(yàn)證平臺(tái)。本文搭建的驗(yàn)證平臺(tái),不僅僅是針對(duì)仲裁模塊,而是適用于整個(gè)芯片的驗(yàn)證平臺(tái),需要能夠支持整個(gè)芯片的所有驗(yàn)證工作。課題中對(duì)驗(yàn)證平臺(tái)的結(jié)構(gòu)、功能,和常用任務(wù)進(jìn)行了詳細(xì)描述。搭建驗(yàn)證平臺(tái)也是本文的主要工作。本文研究的對(duì)象是一款PCI-PCI總線橋,先從芯片的實(shí)際應(yīng)用環(huán)境和基本功能入手,簡(jiǎn)單介紹了相關(guān)的PCI協(xié)議。以固定優(yōu)先級(jí)算法和循環(huán)優(yōu)先級(jí)算法為基礎(chǔ),對(duì)其內(nèi)部仲裁器算法進(jìn)行研究。然后,從驗(yàn)證方法學(xué)的角度,提出了驗(yàn)證方案,并且建立了驗(yàn)證平臺(tái)。最后使用Nc_verilog作為驗(yàn)證工具,通過仿真驗(yàn)證,驗(yàn)證了芯片內(nèi)部仲裁器符合預(yù)期設(shè)計(jì)要求,根據(jù)覆蓋率信息分析了驗(yàn)證工作的可靠性。并且對(duì)芯片初樣進(jìn)行了部分參數(shù)的測(cè)試。本文主要內(nèi)容是第四章和第五章。主要的工作內(nèi)容是芯片驗(yàn)證平臺(tái)的搭建和對(duì)芯片內(nèi)部仲裁器進(jìn)行功能驗(yàn)證。驗(yàn)證平臺(tái)的建立和對(duì)芯片內(nèi)部仲裁器的驗(yàn)證,為其他驗(yàn)證工作和設(shè)計(jì)工作,提供了重要參考價(jià)值。最后,本文中的橋片,通過了Nc-verilog軟件進(jìn)行的前仿驗(yàn)證和后續(xù)的其他驗(yàn)證工作。結(jié)果證明,本文所選用的驗(yàn)證方式,滿足了預(yù)期的驗(yàn)證要求。建立的驗(yàn)證方案,覆蓋了芯片的功能驗(yàn)證要求,對(duì)芯片進(jìn)行了科學(xué)合理的驗(yàn)證仿真。
[Abstract]:With the continuous development of integrated circuits, the variety of product functions and the complexity of the system, the design verification must be more rigorous. We must make more efforts to ensure the correctness of the design. We need to choose the appropriate verification method and efficient verification platform to improve the efficiency of the verification of complex chips. PCI bus is one of the commonly used buses in the system. From the low-end mobile field to the high-end processor, we can find its application. In order to meet the requirements of the application, the system structure is becoming more and more complex. However, on a single PCI bus, The number of loaded devices is limited. In order to achieve bus expansion, bridge devices are usually used to form a hierarchical bus structure. We need a flexible arbitration method to allocate the right to use the bus. The time and resources in the modern IC design are much larger than the design work. So the main workload of this paper is also concentrated in the verification part. The most important work is to build the verification platform. The verification platform built in this paper is not only for the arbitration module, but also for the entire chip verification platform. We need to be able to support all the verification work of the whole chip. The structure, function, and common tasks of the verification platform are described in detail in this paper. Building the verification platform is also the main work of this paper. The object of this paper is a PCI-PCI bus bridge. Starting with the practical application environment and basic functions of the chip, this paper briefly introduces the related PCI protocol. Based on the fixed priority algorithm and the cyclic priority algorithm, the internal arbiter algorithm is studied. From the point of view of verification methodology, the verification scheme is put forward, and the verification platform is established. Finally, Nc_verilog is used as the verification tool, and through simulation verification, it is verified that the internal arbiter of the chip meets the expected design requirements. The reliability of the verification is analyzed according to the coverage information, and some parameters of the chip are tested. The main contents of this paper are 4th and 5th chapters. The main work is the construction of the chip verification platform and the implementation of the chip verification platform. Verify the function of the internal arbiter of the chip, establish the verification platform and verify the internal arbiter of the chip, It provides an important reference value for other verification work and design work. Finally, the bridge piece in this paper has passed the pre-imitation verification and other subsequent verification work carried out by Nc-verilog software. The results show that the verification method chosen in this paper, The proposed verification scheme covers the functional verification requirements of the chip and makes a scientific and reasonable verification simulation of the chip.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN407

【參考文獻(xiàn)】

相關(guān)碩士學(xué)位論文 前1條

1 張亮;PCIe總線物理層的設(shè)計(jì)與驗(yàn)證[D];西安電子科技大學(xué);2013年

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本文編號(hào)：1586299