本文關(guān)鍵詞： 頻率綜合器 Ka波段 DDS PLL 相位噪聲 雜散抑制 捷變頻　出處：《電子科技大學(xué)》2016年碩士論文　論文類型：學(xué)位論文

【摘要】：頻率源是雷達(dá)、通信等電子系統(tǒng)的心臟,并且在制導(dǎo)、射電天文學(xué)、臨床醫(yī)學(xué)等領(lǐng)域也有重要意義,其性能的好壞直接影響各電子系統(tǒng)的指標(biāo)[1]。本文對Ka波段的頻率合成技術(shù)進(jìn)行了雜散、相噪、變頻速度、體積等方面的研究,研制出了綜合性能優(yōu)異的頻率合成源。首先,本文對頻率合成技術(shù)基本理論進(jìn)行了闡述,分析了各種技術(shù)的優(yōu)劣,結(jié)合文章的指標(biāo)要求,并進(jìn)行指標(biāo)初步核算之后,確定了以DDS驅(qū)動PLL為框架結(jié)構(gòu)的方案。然后,在DDS驅(qū)動PLL的基本框架之上,對方案進(jìn)行具體的設(shè)計。最終信號要求為Ka波段,為了降低設(shè)計難度,先實(shí)現(xiàn)X波段的信號輸出,再經(jīng)過3倍頻實(shí)現(xiàn)最終的Ka頻段輸出。為了解決低相噪的要求,采用VCO輸出先下變頻再分頻的方法,使得反饋回路的分頻比大大減小,從而有效降低相噪。為了達(dá)到輸出低雜散的要求,應(yīng)盡量減小DDS的輸出頻率及帶寬。本文先采用固定本振,分頻比N可變的方法來實(shí)現(xiàn),測試發(fā)現(xiàn)某些頻點(diǎn)不能鎖定;然后改用固定分頻比N,本振切換的方法來實(shí)現(xiàn)。最終發(fā)現(xiàn)后者可以解決前者在某些頻點(diǎn)不能鎖定的情況。最后,將系統(tǒng)級聯(lián)測試,得到最終的測試結(jié)果為:輸出頻率為34~36GHz;相位噪聲優(yōu)于-90dBc/Hz@1KHz;雜散優(yōu)于-60dBc;頻率分辨率優(yōu)于53Hz;跳頻時間優(yōu)于7微秒(33.9GHz跳至36GHz),均滿足指標(biāo)要求。
[Abstract]:Frequency sources are the heart of electronic systems such as radar, communications, and are also of great significance in the fields of guidance, radio astronomy, clinical medicine, etc. The performance of Ka-band frequency synthesis technology is studied in the aspects of spurious, phase noise, frequency conversion speed, volume and so on, and a frequency synthesizer with excellent comprehensive performance is developed. In this paper, the basic theory of frequency synthesis technology is expounded, and the advantages and disadvantages of various techniques are analyzed. Combined with the index requirements of the article, and after preliminary accounting of the indicators, the scheme of using DDS driven PLL as the frame structure is determined. Based on the basic frame of DDS driving PLL, the scheme is designed concretely. The final signal is Ka-band. In order to reduce the design difficulty, the X-band signal output is realized first. In order to solve the problem of low phase noise, the method of VCO output first down conversion and then frequency division is adopted, which reduces the frequency division ratio of feedback loop greatly. In order to achieve the requirement of low spurious output, the output frequency and bandwidth of DDS should be reduced as far as possible. Finally, it is found that the latter can solve the situation that the former can not be locked at some frequency points. Finally, the system is cascaded to test. The final test results are as follows: the output frequency is 346GHz; the phase noise is better than -90dBc / Hzr @ 1kHz; the spurious is better than -60dBc; the frequency resolution is better than 53Hz; and the frequency hopping time is better than 7msec 33.9 GHz to 36GHz.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TN74

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相關(guān)期刊論文 前4條

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本文編號：1528389