本文關(guān)鍵詞： CMOS 溫度傳感器 動(dòng)態(tài)范圍 失配誤差 可尋址 CBCM　出處：《浙江大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著半導(dǎo)體工業(yè)的快速發(fā)展,芯片的功耗變得越來越大,另外芯片溫度的分布也不均勻,研究用于監(jiān)控芯片溫度熱點(diǎn)的片上溫度測(cè)量技術(shù)就顯得越來越重要。片上電容測(cè)量技術(shù)既可用于建立互連線的寄生參數(shù)仿真模型又可對(duì)集成電路制造工藝進(jìn)行監(jiān)控,隨著工藝節(jié)點(diǎn)的快速進(jìn)步,其在學(xué)術(shù)界已受到了廣泛關(guān)注。 CMOS智能溫度傳感器是一種片上溫度測(cè)量技術(shù)。為了減小失配誤差和保證較高的輸出動(dòng)態(tài)范圍,本文在0.18um CMOS工藝下,設(shè)計(jì)并流片了一種新型CMOS智能溫度傳感器。和傳統(tǒng)CMOS智能溫度傳感器相比,新結(jié)構(gòu)通過減少電流鏡的使用,以及在兩種運(yùn)行模式之間的切換,在軍用溫度范圍內(nèi),可使輸出達(dá)到90%動(dòng)態(tài)范圍的同時(shí),減小至少66%的失配誤差。 CBCM(Charge-Based Capacitance Measurement)測(cè)試結(jié)構(gòu)是一種具有高精度和簡單測(cè)量過程的片上電容測(cè)量技術(shù),可尋址CBCM測(cè)試結(jié)構(gòu)還具有較快的測(cè)試速度以及較高的面積利用率等優(yōu)點(diǎn)。本文對(duì)CBCM基本結(jié)構(gòu)的測(cè)量誤差進(jìn)行了理論分析和仿真,提出了減小測(cè)量誤差的改進(jìn)措施。另外,在55rnm和28nmCMOS工藝下,對(duì)可尋址CBCM測(cè)試結(jié)構(gòu)進(jìn)行了流片和測(cè)試。基于28rnm工藝的可尋址CBCM電容測(cè)試結(jié)構(gòu)的流片,代表了這一領(lǐng)域的最新進(jìn)展。
[Abstract]:With the rapid development of semiconductor industry, the power consumption of the chip becomes more and more large, and the temperature distribution of the chip is also uneven. It is more and more important to study the on-chip temperature measurement technology which is used to monitor the hot spot of chip temperature. On-chip capacitance measurement technology can be used not only to establish parasitic parameter simulation model of interconnection lines but also to monitor the manufacturing process of integrated circuits. With the rapid progress of process node, it has been paid more and more attention in academia. CMOS intelligent temperature sensor is a kind of on-chip temperature measurement technology. In order to reduce the mismatch error and ensure a high output dynamic range, in this paper, in 0.18um CMOS process, A new type of CMOS intelligent temperature sensor is designed. Compared with the traditional CMOS intelligent temperature sensor, the new structure is in the military temperature range by reducing the use of the current mirror and switching between the two operation modes. The output can reach 90% dynamic range while reducing at least 66% mismatch error. The CBCM(Charge-Based Capacitance measure structure is a high precision and simple measurement technique for measuring capacitance on a chip. Addressable CBCM test structure also has the advantages of fast test speed and high area utilization ratio. This paper analyzes and simulates the measurement error of CBCM basic structure, and puts forward some improvement measures to reduce the measurement error. In 55rnm and 28nm CMOS processes, the addressable CBCM test structure is tested and the flow sheet of the addressable CBCM capacitance test structure based on 28rnm process represents the latest development in this field.
【學(xué)位授予單位】：浙江大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN407

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本文編號(hào)：1513989