本文關(guān)鍵詞：高速低功耗逐次逼近模數(shù)轉(zhuǎn)換器的研究與設(shè)計　出處：《南京郵電大學》2015年碩士論文　論文類型：學位論文

  更多相關(guān)文章： 模數(shù)轉(zhuǎn)換器 逐次逼近型 單位電容 動態(tài)比較器 異步控制技術(shù)

【摘要】：可穿戴移動設(shè)備、紅外傳感器以及無線傳感器網(wǎng)絡(luò)的迅速發(fā)展對電子系統(tǒng)的小型化提出了更高的要求,而模數(shù)轉(zhuǎn)換器是系統(tǒng)中必不可少的部分,其性能直接影響著整個系統(tǒng)的性能。而逐次逼近模數(shù)轉(zhuǎn)換器因其功耗低、面積小、速度適中等特點,長期以來獲得了廣泛的運用,因此其設(shè)計技術(shù)日益受到關(guān)注。本文首先分析了模數(shù)轉(zhuǎn)換器的常見結(jié)構(gòu)及其工作原理,并對它們各自的優(yōu)缺點進行了對比,同時從動態(tài)功耗和非線性參數(shù)INL/DNL角度對現(xiàn)有的逐次逼近模數(shù)轉(zhuǎn)換器里的電容陣列進行了分析與對比,在此基礎(chǔ)上完成了一種6位120MS/s的逐次逼近型模數(shù)轉(zhuǎn)換器電路的設(shè)計。通過對三明治-插指混合型結(jié)構(gòu)單位電容進行設(shè)計與建模,完成了單調(diào)轉(zhuǎn)換電容陣列的設(shè)計,從而有效地改善了模數(shù)轉(zhuǎn)換器的速度與功耗;同時在傳統(tǒng)動態(tài)比較器的頂端采用MOS管恒流源從而有效地提高了比較器的線性度,并對比較器的分辨率和傳輸延時進行了仿真;最后設(shè)計完成了異步控制電路從而實現(xiàn)了異步控制時序,有效地提高了模數(shù)轉(zhuǎn)換器的速度和功耗利用率。通過Cadence設(shè)計平臺完成了整體電路版圖的設(shè)計并進行了前后仿,前仿實驗結(jié)果表明,在1.8V電源電壓下,所設(shè)計的逐次逼近模數(shù)轉(zhuǎn)換器的采樣率為120MS/s,當輸入信號頻率為1.3MHz時,SNR為36.9dB,SNDR為35.8dB,SFDR為48.4dB,ENOB為5.66bit,功耗為2.43mW,FOM值為0.41pJ/Con.step。
[Abstract]:The rapid development of wearable mobile devices, infrared sensors and wireless sensor networks has put forward higher requirements for the miniaturization of electronic systems, and the analog-to-digital converter is an essential part of the system. Its performance directly affects the performance of the whole system, and successive approximation A / D converter has been widely used for a long time because of its low power consumption, small area, moderate speed and so on. Therefore, the design technology has been paid more and more attention. Firstly, this paper analyzes the common structure and working principle of ADC, and compares their advantages and disadvantages. At the same time, the capacitive arrays in successive approximation A / D converters are analyzed and compared from the angle of dynamic power consumption and nonlinear parameter INL/DNL. On this basis, a 6-bit 120MS / s successive approximation analog-to-digital converter circuit is designed. The unit capacitance of sandwich / insert hybrid structure is designed and modeled. The design of monotone conversion capacitor array is completed, which can effectively improve the speed and power consumption of A / D converter. At the same time, the MOS tube constant current source is used at the top of the traditional dynamic comparator to improve the linearity of the comparator effectively, and the resolution and transmission delay of the comparator are simulated. Finally, the asynchronous control circuit is designed to realize the asynchronous control sequence. The efficiency of speed and power efficiency of the ADC is improved effectively. The layout of the whole circuit is designed by using Cadence design platform, and the antecedent simulation results show that. At 1.8V supply voltage, the sampling rate of the successive approximation A / D converter is 120 Ms / s, and the SNR is 36.9 dB when the input signal frequency is 1.3 MHz. The SNDR is 35.8dBnSFDR (48.4dBN) and the power consumption is 2.43mWN (0.41 pJ / Con.Step.)
【學位授予單位】：南京郵電大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN792

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本文編號：1384497