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  本文關(guān)鍵詞：低噪聲斬波Sigma-Delta調(diào)制器的設(shè)計　出處：《哈爾濱工業(yè)大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： Sigma-Delta調(diào)制器 斬波技術(shù) 開關(guān)電容積分器 開關(guān)電容共模反饋

【摘要】：現(xiàn)代社會中數(shù)字領(lǐng)域高速發(fā)展,作為數(shù)字領(lǐng)域與模擬世界的橋梁,模擬數(shù)字轉(zhuǎn)換器(ADC)起到了至關(guān)重要的作用。沒有模擬數(shù)字轉(zhuǎn)換器,自然界中時域與幅值連續(xù)的信號就無法使用數(shù)字領(lǐng)域的信號處理系統(tǒng)進行操作。由于模擬數(shù)字轉(zhuǎn)換器的重要性,人們在這個領(lǐng)域做出了很多探索,使得ADC得到了飛速的發(fā)展。過采樣技術(shù)使得模擬數(shù)字轉(zhuǎn)換器的精度得到了很大的提升,因此過采樣型ADC在工業(yè)設(shè)計生產(chǎn)過程中得到了廣泛的應(yīng)用。調(diào)制器與數(shù)字抽取濾波器是Sigma-Delta數(shù)模轉(zhuǎn)換器的兩大組成部分。其中調(diào)制器完成的是模擬信號量化的功能。本文設(shè)計了一個過采樣型Sigma-Delta調(diào)制器,系統(tǒng)級為單環(huán)四階全前饋型結(jié)構(gòu),該結(jié)構(gòu)能降低對輸入信號幅度的要求。主環(huán)路由積分器級聯(lián)組成,全差分運算放大器采用開關(guān)電容共模反饋。為了得到更好的線性度,本設(shè)計中采用的是一位量化器。時鐘電路采用兩相非交疊時鐘。輸入信號帶寬為200Hz,為抑制低頻噪聲第一級積分器采用斬波技術(shù)消除低頻閃爍噪聲。論文前部分將結(jié)合過采樣調(diào)制器原理闡述一些基本結(jié)構(gòu)的選取思路,論文后部分包括MATLAB中系統(tǒng)級設(shè)計,電路各模塊的設(shè)計與仿真,整體電路的設(shè)計與仿真以及版圖級的設(shè)計。本課題系統(tǒng)級設(shè)計在SIMULINK平臺下進行。電路組成模塊搭建成系統(tǒng)級模塊進行系統(tǒng)級仿真,確定電路基本性能及參數(shù)要求。電路級設(shè)計在CADENCE SPECTRE平臺下進行,完成各模塊的電路級設(shè)計,并對各模塊性能進行仿真,最終完成整體電路搭建并仿真。版圖級設(shè)計在CADENCE平臺下進行,使用標(biāo)準(zhǔn)0.5μm CMOS N阱工藝對整體電路進行版圖設(shè)計并完成后仿。本設(shè)計在帶寬為200Hz的情況下對整體電路進行仿真。輸入信號為21.4Hz,幅度為1V時,仿真的結(jié)果顯示噪聲譜密度中噪聲基底小于-120d B,信噪比達到103d B,有效位數(shù)達16.83位。
[Abstract]:With the rapid development of the digital field in modern society, as the bridge between the digital field and the analog world, the analog-to-digital converter (ADC) plays an important role. There is no analog-to-digital converter. Because of the importance of analog to digital converters, people have made a lot of exploration in this field because of the importance of signal processing systems in the digital domain because of the continuous signal in time domain and amplitude in nature. With the rapid development of ADC, the precision of analog to digital converter has been greatly improved by over-sampling technology. Therefore, oversampling ADC has been widely used in industrial design and production. Modulator and digital decimation filter are two major components of Sigma-Delta digital-to-analog converter, in which modulator is finished. The function of analog signal quantization is obtained. In this paper, an oversampling Sigma-Delta modulator is designed. The system level is a single-loop four-order full-feedforward structure which can reduce the requirement of input signal amplitude. The main loop is composed of integrator cascade. The full differential operational amplifier uses switched capacitor common-mode feedback to obtain better linearity. In this design, a bit quantizer is used. The clock circuit uses a two-phase non-overlapping clock. The input signal bandwidth is 200Hz. In order to suppress the low-frequency noise the chopping technique is used to eliminate the low-frequency scintillation noise in the first stage integrator. The later part of the thesis includes the system-level design of MATLAB, the design and simulation of each module of the circuit. The design and simulation of the whole circuit and the layout level design. The system-level design of the subject is carried out under the SIMULINK platform. The circuit component module is built into the system-level module for system-level simulation. The circuit level design is carried out under the CADENCE SPECTRE platform, the circuit level design of each module is completed, and the performance of each module is simulated. Finally, the whole circuit is built and simulated. The layout level design is carried out under the CADENCE platform. Use of standard 0. 5 渭 m CMOS. The layout of the whole circuit is designed by N-well process and the simulation is completed. The whole circuit is simulated with the bandwidth of 200Hz. The input signal is 21.4Hz. When the amplitude is 1 V, the simulation results show that the noise base is less than -120 dB, the signal-to-noise ratio is 103 dB and the effective bit number is 16.83 bits in the noise spectrum density.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN761

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本文編號：1383196