本文關(guān)鍵詞：一種12位高精度、低功耗電流舵與R-2R電阻混合型DAC的設(shè)計(jì)　出處：《深圳大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 數(shù)模轉(zhuǎn)換器 R2R梯形電阻 電流舵 CMOS集成電路

【摘要】：信號(hào)處理在通信系統(tǒng)、控制系統(tǒng)和計(jì)算機(jī)系統(tǒng)中起著重要作用,信號(hào)處理任務(wù)一般由數(shù)字信號(hào)處理器(DSP)、微控制器(MCU)及微處理器(MPU)實(shí)現(xiàn)。然而自然界中的信號(hào)是模擬信號(hào),所以數(shù)模轉(zhuǎn)換器(DAC)作為連接數(shù)字系統(tǒng)與模擬世界的接口變得不可或缺。移動(dòng)終端的快速發(fā)展促進(jìn)了低功耗數(shù)模轉(zhuǎn)換器的需求,因此,研究高精度、低功耗DAC具有重要意義。本文首先分析了三種常見(jiàn)結(jié)構(gòu)的DAC,通過(guò)比較各種結(jié)構(gòu)的優(yōu)缺點(diǎn),設(shè)計(jì)了一種12位10 MHz的電流舵與R-2R梯形電阻混合型DAC。設(shè)計(jì)采用了5+3+4的分段方式,從結(jié)構(gòu)角度有效地降低了DAC的功耗,其中最高五位采用溫度計(jì)編碼電流舵結(jié)構(gòu),中間三位采用二進(jìn)制編碼電流舵結(jié)構(gòu),最低四位采用R-2R梯形電阻結(jié)構(gòu)。電流舵中的電流源采用共源共柵結(jié)構(gòu),有效地提高了輸出阻抗;同時(shí)在電流源差分開(kāi)關(guān)下面串聯(lián)一對(duì)PMOS管,以降低時(shí)鐘饋通(Clock Feedthrough)對(duì)輸出電壓的影響�？紤]設(shè)計(jì)的DAC高精度的要求,在版圖的設(shè)計(jì)中,采用層次對(duì)稱式電流源選通方式來(lái)消除梯度誤差和對(duì)稱誤差。此外,采用了同步鎖存器電路和交叉點(diǎn)降低電路,有效地減小了DAC的輸出毛刺。本文中設(shè)計(jì)的DAC使用TSMC 0.18μm Mixed-Siganl 1P6M CMOS工藝完成了電路的設(shè)計(jì)和版圖實(shí)現(xiàn),并使用Spectre仿真驗(yàn)證DAC的功能和性能。在1.8 V電源電壓下,差分輸出電壓擺幅為±1.0 V,靜態(tài)功耗為1.3 m A。積分非線性誤差小于0.15 LSB,微分非線性誤差小于0.04 LSB,當(dāng)輸入正弦信號(hào)為300 KHz、采樣時(shí)鐘為10 MHz時(shí)的無(wú)雜波動(dòng)態(tài)范圍(SFDR)約為68 d B。測(cè)試結(jié)果表明,本文設(shè)計(jì)的12位DAC的DNL±9.5LSB,INL±13.5LSB。
[Abstract]:Signal processing plays an important role in communication system, control system and computer system. Microcontroller (MCU) and microprocessor (MPU) are implemented. However, signals in nature are analog signals. So DAC) as the interface between digital system and analog world becomes indispensable. The rapid development of mobile terminal promotes the demand of low power DAC. Low power DAC is of great significance. Firstly, this paper analyzes three kinds of common structure DACs, and compares the advantages and disadvantages of each structure. A 12-bit 10 MHz current rudder and R-2R trapezoidal resistance hybrid DAC are designed. The design adopts 534 piecewise mode, which can effectively reduce the power consumption of DAC from the point of view of structure. Among them, the highest five are thermometer coded current rudder structure, the middle three are binary coded current rudder structure, the lowest four are R-2R trapezoidal resistance structure, and the current source in the current rudder is a common source common-grid structure. The output impedance is improved effectively; At the same time, a pair of PMOS transistors are connected in series under the current source differential switch. In order to reduce the impact of clock feed through (clock feed through) on the output voltage. Consider the high accuracy of the DAC design in the layout design. The hierarchical symmetric current source is used to eliminate gradient error and symmetry error. In addition, synchronous latch circuit and crossing point lowering circuit are used. The output burr of DAC is reduced effectively. The DAC designed in this paper uses TSMC 0.18 渭 m Mixed-Siganl 1P6M. CMOS process completes the circuit design and layout implementation. The function and performance of DAC are verified by Spectre simulation. The differential output voltage swing is 鹵1.0 V at 1.8V power supply voltage. The static power consumption is 1.3 Ma, the integral nonlinear error is less than 0. 15 LSBs, the differential nonlinear error is less than 0. 04 LSBs, and the input sinusoidal signal is 300 KHz. When the sampling clock is 10 MHz, the dynamic range of clutter free SFDR is about 68 dB. The test results show that the DNL 鹵9.5 LSB of the 12-bit DAC is designed in this paper. INL 鹵13.5LSB.
【學(xué)位授予單位】：深圳大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN792;TN911.7

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本文編號(hào)：1383126