【摘要】：隨著電子技術(shù)的高速發(fā)展和國家對電子產(chǎn)業(yè)發(fā)展的需要,開關(guān)電源的需求量得到了巨大的增長,人們對電源管理類芯片的性能和功能也提出了更多和更高的要求。小型化、高效率、抗EMI、少的外圍器件、低壓大電流等成為了電源芯片設(shè)計(jì)中日益重要的研究課題。本論文是基于電源發(fā)展趨勢的需求并結(jié)合實(shí)驗(yàn)室現(xiàn)有科研成果,研究可多路并聯(lián)輸出的同步降壓型DC-DC轉(zhuǎn)換器芯片組的設(shè)計(jì)及實(shí)現(xiàn)。本文詳細(xì)分析了Buck型DC-DC轉(zhuǎn)換器的基本工作原理,對其穩(wěn)態(tài)下各輸出點(diǎn)的工作波形做了詳細(xì)的分析,對其傳輸關(guān)系做完整的推導(dǎo),對芯片組并聯(lián)使用時(shí)最優(yōu)控制方案和減小紋波方法理論上做了簡要的闡述。在此基礎(chǔ)上設(shè)計(jì)了一款可實(shí)現(xiàn)多路并聯(lián)輸出的低紋波率同步降壓型轉(zhuǎn)換器。該轉(zhuǎn)換器采用PWM調(diào)制的峰值電流模控制方式,提高了系統(tǒng)的瞬態(tài)反應(yīng)速度,且具有輸出電感較小、補(bǔ)償電路簡單、增益帶寬大、易于均流等優(yōu)點(diǎn)。此款芯片可以實(shí)現(xiàn)單通道的大電流輸出和兩款該芯片并聯(lián)的雙通道輸出,或者更多該同類型芯片并聯(lián)實(shí)現(xiàn)更大電流的輸出。設(shè)計(jì)中充分考慮了多個(gè)DC-DC轉(zhuǎn)換器并聯(lián)時(shí),如何實(shí)現(xiàn)芯片組之間電流的均分,以減輕熱損耗,改善系統(tǒng)的反應(yīng)速度,延長芯片組中各子模塊的壽命。芯片內(nèi)部集成了鎖相環(huán)電路和分頻電路,可以使芯片在多相模式下工作,以有效的減小在多個(gè)芯片并聯(lián)使用時(shí)所需的大容量電容,降低大電流工作下輸出和輸入電壓紋波的大小。而且內(nèi)部集成的鎖相環(huán)同步電路和采用的主從均流控制方式,能夠有效的實(shí)現(xiàn)輸出電流的均分。對于芯片工作在輕負(fù)載時(shí),可以根據(jù)客戶在輸出電壓紋波大小和效率之間的需要,選擇兩種不同的工作方式:強(qiáng)制脈沖寬度調(diào)制模式(FCCM)或脈沖跳變調(diào)制模式(PSM)。針對芯片寬輸入和寬輸出范圍,芯片設(shè)計(jì)了一種二次斜坡補(bǔ)償技術(shù),相對于普通的一次線性斜坡補(bǔ)償,進(jìn)一步提高了芯片的整體的帶載能力以及消除了占空比大于50%時(shí)出現(xiàn)的亞諧波振蕩、開環(huán)不穩(wěn)定和對噪聲比較敏感等缺點(diǎn)。同時(shí)設(shè)計(jì)中采用了動(dòng)態(tài)箝位電路,對誤差放大器的輸出端采用了動(dòng)態(tài)電壓進(jìn)行限幅,相對于固定的箝位電壓,有效的避免了斜坡補(bǔ)償對芯片帶載能力的影響。此外,芯片內(nèi)部還集成了欠壓保護(hù)、過壓保護(hù)、過流保護(hù)、外部軟啟動(dòng)電路等多種功能。論文對該款芯片選用BCD工藝的原因也做了說明,針對芯片外圍器件的選擇和影響芯片工作效率的因素,論文同樣做了比較詳細(xì)的分析。本文研究的可實(shí)現(xiàn)多路并聯(lián)均流降壓型DC-DC轉(zhuǎn)換器芯片組是基于0.35um BCD工藝設(shè)計(jì),在Cadence下完成了芯片子模塊電路和整體功能的仿真。單個(gè)芯片輸入電壓范圍4.5V~26.5V,單通道最大可以拉8A負(fù)載電流,雙通道并聯(lián)組成的輸出,能使輸出電流達(dá)到16A,單款芯片效率可達(dá)95%,符合設(shè)計(jì)要求。
[Abstract]:With the rapid development of electronic technology and the development of national electronic industry, the demand for switching power supply has been greatly increased, and the performance and function of power management chips have been put forward more and higher requirements. Miniaturization, high efficiency, low EMI, resistance, low voltage and high current have become increasingly important research topics in power chip design. This paper is based on the development trend of power supply and combined with the existing scientific research results of the laboratory to study the design and implementation of synchronous step-down DC-DC converter chipset with multi-parallel output. In this paper, the basic working principle of Buck type DC-DC converter is analyzed in detail, the working waveform of each output point in steady state is analyzed in detail, and the transmission relation is deduced. The optimal control scheme and the method of reducing ripple in parallel operation of chipset are briefly described in theory. Based on this, a low ripple rate synchronous step-down converter is designed. The converter adopts the peak current mode control method of PWM modulation, which improves the transient response speed of the system, and has the advantages of small output inductance, simple compensation circuit, large gain bandwidth and easy current sharing. This chip can realize the high current output of single channel and the double channel output of two parallel chips, or more of the same type chip can realize larger current output in parallel. In order to reduce the heat loss, improve the reaction speed of the system and prolong the life of each sub-module of the chipset, the design takes full account of how to realize the equalization of current between the chipsets when several DC-DC converters are connected in parallel. The PLL circuit and the frequency divider circuit are integrated inside the chip, which can make the chip work in the multi-phase mode, so as to effectively reduce the large capacity capacitors needed for the parallel use of multiple chips. Reduce the output and input voltage ripple size under high current operation. The internal integrated PLL synchronization circuit and the master-slave current sharing control method can effectively realize the average output current distribution. When the chip works under light load, two different modes of operation can be selected according to the customer's demand between output voltage ripple size and efficiency: forced pulse width modulation mode (FCCM) or pulse jump modulation mode (PSM). For the wide input and wide output range of the chip, a secondary ramp compensation technique is designed, which is relative to the common linear ramp compensation. It further improves the overall load capacity of the chip and eliminates the shortcomings of sub-harmonic oscillation, open-loop instability and sensitivity to noise when the duty cycle is larger than 50. At the same time, the dynamic clamping circuit is used in the design, and the dynamic voltage is used to limit the output of the error amplifier. Compared with the fixed clamping voltage, the slope compensation can effectively avoid the influence of the ramp compensation on the chip's load capacity. In addition, there are many functions such as under-voltage protection, over-current protection, external soft start circuit and so on. This paper also explains the reason why the chip uses BCD technology. The paper also makes a detailed analysis on the choice of chip peripheral devices and the factors that affect the efficiency of the chip. In this paper, the chipset of DC-DC converter with parallel current and voltage sharing is designed based on 0.35um BCD technology. The circuit and the whole function of the chip are simulated under Cadence. The input voltage of a single chip ranges from 4.5 V to 26.5V, and the maximum load current of 8A can be pulled by a single channel. The output current of two parallel channels can reach 16A, and the efficiency of a single chip can reach 95A, which meets the design requirements.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TM46

【參考文獻(xiàn)】

相關(guān)期刊論文 前2條

1 畢超;肖飛;謝楨;陳明;;交錯(cuò)并聯(lián)技術(shù)在并聯(lián)DC-DC變換器紋波抑制中的分析與應(yīng)用[J];電氣自動(dòng)化;2013年04期

2 路秋生;電流型變換器工作原理和斜坡補(bǔ)償[J];儀器儀表學(xué)報(bào);2001年S2期

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本文編號：2402828