【摘要】：隨著便攜式電子產品越來越普及，人們對電源管理芯片的需求越來越多。作為電源管理芯片龐大家族中的一員，低壓差（LDO，Low Drop-Out）線性穩(wěn)壓器以其極低的輸入輸出電壓差、小的輸出紋波、低的輸出噪聲、低靜態(tài)電流以及低成本等優(yōu)勢，廣泛應用于便攜式電子產品中，比如，醫(yī)療、無線通訊工具、音頻設備、PDA（個人數字助理）以及汽車電子等。目前，LDO線性穩(wěn)壓器正朝著更小尺寸、更低功耗、更高效率等方向發(fā)展，應用前景十分廣闊，因此深入研究高性能的LDO線性穩(wěn)壓器仍具有十分重要的現實意義。 本文首先分析了電源管理芯片的研究價值和對比了LDO線性穩(wěn)壓器與其它穩(wěn)壓器的優(yōu)缺點；然后研究了LDO線性穩(wěn)壓器的系統(tǒng)結構，并對系統(tǒng)中各模塊的性能參數進行了研究；分別設計了穩(wěn)壓器的子模塊，并給出了仿真結果；研究了LDO線性穩(wěn)壓器的穩(wěn)定性問題，給出了幾種頻率補償方法；最后進行了整體仿真。本文設計的LDO低壓差線性穩(wěn)壓器有五個主要部分組成，分別是參考基準，誤差放大器，功率管，反饋網絡以及保護電路。其中，，重點設計了參考基準電壓源，通過引入高階補償，獲得了較低溫度系數的帶隙基準；設計了帶密勒補償的誤差放大器，提高了LDO線性穩(wěn)壓芯片的整體性能；研究了功率管的工作原理，選取了合適的管子尺寸；為了保證整個系統(tǒng)的穩(wěn)定性，研究分析了幾種常用的頻率補償方法；最后，為了保障芯片工作的安全性，設計了相關的保護電路，包括過流保護電路和過壓保護電路。在文章的最后對整個LDO線性穩(wěn)壓器進行了仿真分析。 本文利用Cadence公司的Spectre仿真軟件，采用上華CSMC0.5μm CMOS工藝模型庫，在室溫下，對所設計的LDO進行了整體仿真。仿真結果表明：LDO線性穩(wěn)壓器可在3V-5V電源電壓下工作，典型輸出電壓為3V，最低漏失電壓僅為60mV，線性調整率和負載調整率分別為0.044%和0.177%，電源紋波抑制比為-64dB，另外該設計還具有良好的瞬態(tài)特性和交流特性，能夠滿足設計要求。
[Abstract]:With the increasing popularity of portable electronic products, there is more and more demand for power management chips. As a member of a large family of power management chips, low voltage difference (LDO,Low Drop-Out) linear regulators have the advantages of very low input and output voltage difference, small output ripple, low output noise, low static current and low cost. Widely used in portable electronic products, such as medical, wireless communication tools, audio equipment, PDA (personal digital assistant) and automotive electronics. At present, LDO linear regulators are developing towards smaller size, lower power consumption, higher efficiency and so on, and the application prospect is very broad. Therefore, it is still of great practical significance to study the high performance LDO linear regulators. This paper first analyzes the research value of the power management chip and compares the advantages and disadvantages between the LDO linear regulator and other regulators, then studies the system structure of the LDO linear voltage regulator, and studies the performance parameters of each module in the system. The sub-modules of the regulator are designed, and the simulation results are given. The stability of the LDO linear regulator is studied, and several frequency compensation methods are given. Finally, the overall simulation is carried out. The LDO low voltage difference linear regulator designed in this paper is composed of five main parts, which are reference, error amplifier, power transistor, feedback network and protection circuit. Among them, the reference voltage source is designed, the bandgap reference with low temperature coefficient is obtained by introducing high-order compensation, the error amplifier with Miller compensation is designed, and the overall performance of LDO linear voltage stabilized chip is improved. In order to ensure the stability of the whole system, several common frequency compensation methods are studied and analyzed. Finally, in order to ensure the security of the chip, the related protection circuits are designed, including over-current protection circuit and over-voltage protection circuit. At the end of the paper, the whole LDO linear regulator is simulated and analyzed. In this paper, using the Spectre simulation software of Cadence Company and CSMC0.5 渭 m CMOS process model library of Shanghai China, the overall simulation of the designed LDO is carried out at room temperature. The simulation results show that the LDO linear voltage regulator can work under the 3V-5V power supply voltage. The typical output voltage is 3 V, the lowest leakage voltage is only 60 MV, the linear adjustment rate and load adjustment rate are 0.044% and 0.177%, respectively. The ripple suppression ratio of power supply is -64dB. in addition, the design also has good transient and AC characteristics, which can meet the design requirements.
【學位授予單位】：武漢科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TM44

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