電壓模式PFM升壓DC-DC轉(zhuǎn)換器設(shè)計(jì)
本文選題:升壓型 切入點(diǎn):PFM 出處:《哈爾濱工業(yè)大學(xué)》2014年碩士論文
【摘要】:現(xiàn)如今便攜式電子產(chǎn)品正逐漸取代大體積的電子產(chǎn)品進(jìn)入人們的日常生活、工作和學(xué)習(xí)中,這些便攜式電子產(chǎn)品正常工作需要高性能的電源管理芯片。體積小、效率高、穩(wěn)壓范圍寬、噪聲小的開(kāi)關(guān)電源,在便攜式電子產(chǎn)品中得到了廣泛的應(yīng)用。 論文針對(duì)市場(chǎng)需求日益增長(zhǎng)的電源管理芯片,對(duì)電壓模式PFM升壓DC-DC轉(zhuǎn)換器進(jìn)行了研究。重點(diǎn)研究了基準(zhǔn)電壓源、比較器電路、頻率可調(diào)環(huán)形振蕩器、啟動(dòng)電路、限流保護(hù)電路等開(kāi)關(guān)電源中必備的幾個(gè)功能模塊,并完成了整體電路設(shè)計(jì)和仿真。 論文基于脈沖頻率調(diào)制方式實(shí)現(xiàn)升壓DC-DC轉(zhuǎn)換,控制電路采樣輸出電壓,根據(jù)輸出電壓的不同,產(chǎn)生頻率可變的脈沖信號(hào)作用于功率開(kāi)關(guān)管柵極,控制其導(dǎo)通與關(guān)斷的時(shí)間,進(jìn)而維持輸出電壓穩(wěn)定。為了減小系統(tǒng)處于空載或輕負(fù)載時(shí)損耗,引入跳周期調(diào)制,使脈沖信號(hào)在負(fù)載較輕時(shí)跳過(guò)一定的周期,,功率開(kāi)關(guān)管在這段時(shí)間內(nèi)保持關(guān)斷,使系統(tǒng)處于空閑狀態(tài)。 根據(jù)升壓型DC-DC轉(zhuǎn)換器輸出電壓高于輸入電壓并且穩(wěn)定的特點(diǎn),采用輸出電壓作為芯片中各個(gè)模塊的電源電壓,為了解決系統(tǒng)起始階段輸出電壓較低,不能滿足模塊正常工作的問(wèn)題,設(shè)計(jì)了基于電容自舉原理的啟動(dòng)電路。為了給電路中電壓比較器和遲滯比較器提供穩(wěn)定的參考電壓,設(shè)計(jì)了二階曲率補(bǔ)償帶隙基準(zhǔn)電路。為了實(shí)現(xiàn)脈沖頻率可調(diào),設(shè)計(jì)了可以產(chǎn)生兩種頻率的環(huán)形振蕩器,通過(guò)控制其延遲單元尾電流的大小產(chǎn)生不同頻率。為了根據(jù)輸出電壓的采樣信號(hào)和基準(zhǔn)電壓大小,產(chǎn)生控制信號(hào)作用于振蕩器使其產(chǎn)生不同的頻率,設(shè)計(jì)了采用兩級(jí)運(yùn)算放大器和輸出級(jí)構(gòu)成電壓比較器。當(dāng)輸出電壓上升到一定值時(shí),為了控制振蕩器跨過(guò)一定的周期,設(shè)計(jì)了遲滯比較器。 論文設(shè)計(jì)的電壓模式PFM升壓DC-DC轉(zhuǎn)換器基于SMIC0.18μm工藝實(shí)現(xiàn),在輸入電壓為1.8V,負(fù)載電流0~100mA范圍內(nèi)時(shí),輸出電壓都基本穩(wěn)定在3V,紋波小于50mV,輸入電壓允許范圍達(dá)到了0.9V~2V,最大工作頻率為400kHz。在輕負(fù)載時(shí)效率在90%以上,重載時(shí)效率也達(dá)到了80%。系統(tǒng)的允許溫度工作范圍為-30oC~100oC。
[Abstract]:Nowadays, portable electronic products are gradually replacing bulky electronic products in their daily life, working and studying. These portable electronic products need high-performance power management chips to work normally. Switching power supply with wide voltage range and low noise is widely used in portable electronic products. Aiming at the increasing market demand of power supply management chip, this paper studies the voltage-mode PFM boost DC-DC converter, focusing on the reference voltage source, comparator circuit, frequency adjustable ring oscillator, starting circuit, and so on. The circuit design and simulation are completed. Based on the pulse frequency modulation, this paper realizes the boost DC-DC conversion, and the output voltage of the control circuit is sampled. According to the different output voltage, the pulse signal with variable frequency acts on the gate of the power switch tube, and controls the time of its turn-on and turn-off. In order to reduce the loss when the system is under no load or light load, the hopping period modulation is introduced to make the pulse signal skip a certain period when the load is lighter, and the power switch tube remains off during this period. Keep the system idle. According to the characteristics that the output voltage of the boost DC-DC converter is higher than the input voltage and stable, the output voltage is used as the power supply voltage of each module in the chip, in order to solve the problem that the output voltage is low in the initial stage of the system, The starting circuit based on the principle of capacitive bootstrap is designed to provide a stable reference voltage for the voltage comparator and hysteresis comparator in the circuit. The second order curvature compensated bandgap reference circuit is designed. In order to realize the adjustable pulse frequency, a ring oscillator with two frequencies is designed. Different frequencies are generated by controlling the size of the tail current of the delay cell. In order to produce control signals acting on the oscillator to produce different frequencies according to the sampling signal of the output voltage and the magnitude of the reference voltage, A voltage comparator consisting of a two-stage operational amplifier and an output stage is designed. When the output voltage rises to a certain value, a hysteresis comparator is designed to control the oscillator to cross a certain period. The voltage-mode PFM boost DC-DC converter designed in this paper is based on SMIC0.18 渭 m technology. When the input voltage is 1.8 V and the load current is 0~100mA, The output voltage is basically stable at 3 V, the ripple is less than 50 MV, the input voltage is within 0.9V / 2 V and the maximum operating frequency is 400 kHz. The efficiency is over 90% at light load and 80% at heavy load. The allowable temperature range of the system is -30oC ~ (10) oC.
【學(xué)位授予單位】:哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】:碩士
【學(xué)位授予年份】:2014
【分類號(hào)】:TM46
【參考文獻(xiàn)】
相關(guān)期刊論文 前10條
1 程夢(mèng)璋;景為平;;CMOS環(huán)型壓控振蕩器的設(shè)計(jì)[J];電子科技大學(xué)學(xué)報(bào);2009年02期
2 李辛毅;姚素英;趙毅強(qiáng);;一種高速低功耗遲滯CMOS比較器的分析與設(shè)計(jì)[J];電路與系統(tǒng)學(xué)報(bào);2009年03期
3 越建統(tǒng) ,薛紅兵 ,梁樹(shù)坤;電源產(chǎn)業(yè)及電源技術(shù)的發(fā)展趨勢(shì)[J];電氣時(shí)代;2004年11期
4 李新;牟鑫鑫;;低輸入電壓DC-DC升壓轉(zhuǎn)換器的啟動(dòng)電路[J];電子設(shè)計(jì)工程;2010年05期
5 穆辛;周新田;張慧慧;金銳;劉鉞楊;吳郁;;一種施密特觸發(fā)器型壓控振蕩器的設(shè)計(jì)與仿真[J];電子科技;2014年04期
6 侯清江;張黎強(qiáng);許棟剛;;開(kāi)關(guān)電源的基本原理及發(fā)展趨勢(shì)探析[J];制造業(yè)自動(dòng)化;2010年09期
7 鄒雪城;涂熙;騫海榮;;低壓差穩(wěn)壓電源的折返式限流保護(hù)電路的設(shè)計(jì)[J];通信電源技術(shù);2007年04期
8 雷媛媛;吳勝益;;試論開(kāi)關(guān)電源技術(shù)的發(fā)展[J];通信電源技術(shù);2008年04期
9 孟建輝;;開(kāi)關(guān)電源的基本原理及發(fā)展趨勢(shì)[J];通信電源技術(shù);2009年06期
10 劉樹(shù)林;劉健;楊銀玲;趙新毅;;Boost變換器的能量傳輸模式及輸出紋波電壓分析[J];中國(guó)電機(jī)工程學(xué)報(bào);2006年05期
本文編號(hào):1653429
本文鏈接:http://sikaile.net/kejilunwen/dianlilw/1653429.html