本文關(guān)鍵詞：具有數(shù)字校準(zhǔn)功能的雙相并聯(lián)Buck型DC-DC芯片的設(shè)計(jì)　出處：《西安電子科技大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 降壓型 數(shù)字校準(zhǔn) 鎖相環(huán) 雙相并聯(lián)

【摘要】：隨著集成電路技術(shù)的快速發(fā)展以及便攜式電子設(shè)備的廣泛應(yīng)用,對電子市場中的電源管理設(shè)備的要求也越來越高。其中開關(guān)電源以外圍器件少、效率高和體積小的優(yōu)點(diǎn)在電源管理類芯片中得到青睞,而傳統(tǒng)的開關(guān)電源依然存在著帶載能力不足、輸出電壓不精確、紋波大等缺陷,因此研究能滿足大負(fù)載、低功耗、小紋波和高準(zhǔn)確度應(yīng)用要求的電源管理芯片意義重大。本文基于降壓型DC-DC轉(zhuǎn)換器基本工作原理,提出了具有數(shù)字校準(zhǔn)功能的雙相并聯(lián)Buck型DC-DC芯片的設(shè)計(jì)與實(shí)現(xiàn)。該芯片采用連續(xù)工作模式和峰值電流模式控制的脈沖寬度調(diào)制方式,具有對大負(fù)載的快速瞬態(tài)響應(yīng)能力、片外易補(bǔ)償、輸出電壓可校準(zhǔn)等特點(diǎn)。論文介紹了Buck型DC-DC的基本工作原理及各種工作模式下的穩(wěn)態(tài)分析,在此基礎(chǔ)上引出了外部數(shù)字校準(zhǔn)功能,并對其進(jìn)行了詳細(xì)的理論分析。芯片已通過仿真驗(yàn)證可以滿足對輸出電壓進(jìn)行±15%幅度內(nèi)的校正,減小了由內(nèi)部基準(zhǔn)電壓不準(zhǔn)確或者輸出線損導(dǎo)致的輸出誤差,得到精確的輸出電壓。同時論文就雙相并聯(lián)大負(fù)載的應(yīng)用詳細(xì)分析了可用于外同步的鎖相環(huán)技術(shù)和雙相并聯(lián)技術(shù),鎖相環(huán)技術(shù)使得內(nèi)部時鐘可與外部時鐘同步,實(shí)現(xiàn)100kHz~1MHz的頻率鎖定范圍,滿足雙相并聯(lián)應(yīng)用中兩個芯片的時鐘同步,相位相差180度。通過多主控器模式和單主控器模式的均流技術(shù),可以實(shí)現(xiàn)兩個芯片并聯(lián)應(yīng)用時,電感電流紋波的抵消和小紋波電壓的輸出,解決了小輸入輸出電容大負(fù)載12A輸出和穩(wěn)定性的折中。論文首先對各種類型的開關(guān)電源作了簡要的概述,并針對降壓型DC-DC轉(zhuǎn)換器的拓?fù)浣Y(jié)構(gòu)和工作原理進(jìn)行了詳細(xì)的分析,同時對降壓型DC-DC轉(zhuǎn)換器的斷續(xù)導(dǎo)通和連續(xù)導(dǎo)通兩種工作模式下的穩(wěn)態(tài)特性以及系統(tǒng)的調(diào)制方式進(jìn)行了比對和詳細(xì)描述;然后重點(diǎn)介紹了數(shù)字校準(zhǔn)功能、鎖相環(huán)技術(shù)以及雙相并聯(lián)技術(shù);最后對芯片的整體功能、外圍器件的選擇和穩(wěn)定性進(jìn)行了分析,并以帶隙基準(zhǔn)電壓模塊、電流采樣模塊和脈沖寬度調(diào)制比較器模塊為例簡要分析了芯片子模塊的設(shè)計(jì)過程及原理,同時簡單介紹了芯片在版圖設(shè)計(jì)過程中需要注意的幾個方面。本文所提出的具有數(shù)字校準(zhǔn)功能的雙相并聯(lián)Buck型DC-DC芯片,目前已基于0.35μm BCD工藝,在Cadence軟件平臺上,利用Spectre仿真環(huán)境在不同的工藝角和不同的環(huán)境溫度下對單芯片的子模塊和整體、數(shù)字校準(zhǔn)功能以及雙相并聯(lián)大負(fù)載應(yīng)用完成了仿真驗(yàn)證,仿真結(jié)果證明該芯片可以實(shí)現(xiàn)對輸出電壓的數(shù)字校準(zhǔn)和雙相并聯(lián)大負(fù)載的應(yīng)用。
[Abstract]:With the rapid development of integrated circuit technology and the wide application of portable electronic equipment, the requirement of power management equipment in electronic market is more and more high. The advantages of high efficiency and small size are favored in the power management chip, but the traditional switching power supply still has shortcomings such as insufficient load capacity, inaccurate output voltage, large ripple, so the research can meet the heavy load. Low power consumption, small ripple and high accuracy requirements of the power management chip is of great significance. This paper is based on the basic principle of the step-down DC-DC converter. This paper presents the design and implementation of a dual-phase parallel Buck DC-DC chip with digital calibration function, which adopts the pulse width modulation mode controlled by continuous operation mode and peak current mode. It has the characteristics of fast transient response to large load, easy compensation out of chip and calibrating output voltage. This paper introduces the basic working principle of Buck type DC-DC and the steady state analysis under various working modes. On this basis, the external digital calibration function is introduced, and the detailed theoretical analysis is given. The chip has been verified by simulation to achieve 鹵15% amplitude correction of the output voltage. The output error caused by the inaccuracy of the internal reference voltage or the output line loss is reduced. At the same time, the paper analyzes in detail the phase-locked loop technology and the two-phase parallel connection technology, which can synchronize the internal clock and the external clock. The frequency locking range of 100kHz 1MHz is realized, and the clock synchronization between the two chips is satisfied, and the phase difference is 180 degrees. The current sharing technology of multi-master controller mode and single master controller mode is adopted. When two chips are applied in parallel, the current ripple cancellation and the output of small ripple voltage can be realized. The tradeoff between 12A output and stability of small input output capacitor with large load is solved. Firstly, various types of switching power supply are briefly summarized in this paper. The topology and working principle of the reduced voltage DC-DC converter are analyzed in detail. At the same time, the steady-state characteristic and modulation mode of DC-DC converter are compared and described in detail. Then the digital calibration function, phase-locked loop technology and two-phase parallel technology are introduced. Finally, the overall function of the chip, the selection and stability of peripheral devices are analyzed, and the bandgap voltage module is used as reference. The current sampling module and the pulse width modulation comparator module are used as examples to analyze the design process and principle of the chip sub-module. At the same time, this paper briefly introduces several aspects that should be paid attention to in the process of layout design. A dual-phase parallel Buck DC-DC chip with the function of digital calibration is proposed in this paper. At present, based on 0.35 渭 m BCD process, it is on the Cadence software platform. The Spectre simulation environment is used to verify the sub-module and the whole module of the single chip, the digital calibration function and the dual-phase parallel large load application under different process angles and different ambient temperature. The simulation results show that the chip can realize the digital calibration of output voltage and the application of double phase parallel large load.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TM46

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本文編號：1408643