本文選題：單片集成 + 封裝電感�。� 參考：《合肥工業(yè)大學》2016年碩士論文

【摘要】：在目前的半導體行業(yè)中,正如摩爾定律所描述,半導體工藝越來越先進,器件的尺寸越來越小,除了追求速度,另外一個重要方面就是小型化,即單片集成。單片集成的開關電源,符合當下消費電子行業(yè)的主流發(fā)展趨勢,而且可以將內部系統(tǒng)與由封裝寄生參數(shù)引起的外部諧振電壓相隔離,降低芯片外部干擾對內部系統(tǒng)的影響。電感型開關電源中,片外電感占據(jù)了PCB的很大一部分空間,此外在開關電源中,高效率也是學者們一直追求和研究的非常重要的性能參數(shù),所以,對于集成片上電感高效率開關電源的研究就變得非常具有吸引力。本文主要提出一種片上集成電感高效率降壓型直流-直流轉換器換器(Buck DC-DC Converter)。轉換器在1.8V輸入電壓下得到0.9V輸出電壓,開關頻率提高到了50MHz,最大負載電流可達500mA,輸出電壓最大紋波小于100mV。本文采用一種新穎的封裝電感來實現(xiàn)電感的片上集成,封裝電感利用焊線(Bond-Wire)和封裝引線(Lead Frame)的寄生電感構成所需的功率級電感,這種電感既可以節(jié)省芯片面積,同時具有較高的Q值,可提高變換器的轉換效率；另外,本文采用了雙模式控制策略：PWMPSM,使轉換器在整個負載范圍內都有較高的轉換效率。按照設計要求,完成了各個小模塊的設計,同時還提出了一些新穎的電路模塊,例如過零檢測模塊和PSM控制模塊等。本文基于SMIC 0.18μm混合信號工藝庫,使用Cadence Spectre軟件對各個小模塊和整個環(huán)路進行仿真驗證。仿真結果顯示本文設計的電路符合設計要求,最后對設計的芯片進行了測試,峰值效率為71%,在負載電流為10mA的情況下,仍然有57%的轉換效率。
[Abstract]:In the current semiconductor industry, as described by Moore's law, semiconductor technology is becoming more and more advanced and the device size is becoming smaller and smaller. In addition to the pursuit of speed, another important aspect is miniaturization, that is, monolithic integration. The single-chip integrated switching power supply is in line with the mainstream trend of the consumer electronics industry and can isolate the internal system from the external resonant voltage caused by the parasitic parameters of the package and reduce the impact of the external interference on the internal system. In the inductive switching power supply, the off-chip inductance occupies a large part of the space of PCB. In addition, in the switching power supply, high efficiency is also a very important performance parameter that scholars have been pursuing and studying, so, The study of on-chip inductor switching power supply becomes very attractive. In this paper, an on-chip integrated inductor with high efficiency step-down DC / DC converter and buck DC-DC converter is presented. The output voltage of the converter is 0.9V at the input voltage of 1.8V, the switching frequency is increased to 50MHz, the maximum load current can reach 500mAand the maximum ripple of the output voltage is less than 100mV. In this paper, a novel package inductor is used to realize the on-chip integration of the inductor. The parasitic inductance of the package inductor is composed of the parasitic inductance of the soldering wire Bond-Wireand the encapsulated lead frame. This inductance can not only save the area of the chip, but also save the chip area. At the same time, the conversion efficiency of the converter can be improved with higher Q value. In addition, the dual-mode control strategy: PWMPSMis used in this paper, which makes the converter have higher conversion efficiency in the whole load range. According to the design requirements, the design of each module is completed, and some novel circuit modules, such as zero-crossing detection module and PSM control module, are also proposed. Based on the SMIC 0.18 渭 m mixed signal process library, the Cadence Spectre software is used to simulate each small module and the whole loop. The simulation results show that the designed circuit meets the requirements of the design. Finally, the designed chip is tested, the peak efficiency is 71 and the conversion efficiency is still 57% when the load current is 10mA.
【學位授予單位】：合肥工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2016
【分類號】：TM46

【相似文獻】

相關期刊論文 前10條

1 易榮;趙爭鳴;;受雜散電感影響的大容量變換器中IGCT關斷特性研究[J];中國電機工程學報;2007年31期

2 梁美;鄭瓊林;李艷;賈鵬宇;;電流連續(xù)型雙電感Boost類拓撲[J];電工技術學報;2013年12期

3 嚴開沁;李竹筠;陳乾宏;;基于PFC變換器的非線性電感的設計研究[J];電工電能新技術;2013年03期

4 Jean-Paul LOUVEL;Joel TURCHI;;減小電感尺寸,設計纖薄的PFC電源段[J];電子設計技術;2010年09期

5 王凡;王志強;;分立電感無橋Boost PFC拓撲的諧振現(xiàn)象研究[J];電源技術應用;2006年11期

6 楊帆;陳志輝;;電感設計[J];電源技術應用;2007年03期

7 王斌;王鳳巖;許建平;;單電感多輸出變換器研究[J];電源世界;2008年02期

8 王鳳巖;任黎立;王斌;許建平;;單電感多輸出變換器研究[J];通信電源技術;2008年03期

9 張曉峰;周雒維;羅全明;盧偉國;;磁集成雙頻DC/DC變換器[J];電工技術學報;2010年01期

10 劉珂;菅洪彥;黃晨靈;唐長文;閔昊;;多電流路徑抑制片上電感電流擁擠效應[J];半導體學報;2006年09期

相關會議論文 前3條

1 高，

本文編號：1854108