路由器SoC系統(tǒng)架構(gòu)的研究與設(shè)計(jì)
[Abstract]:As the core equipment of Internet network, routers play a key role in the performance of the whole network system. On the one hand, with the arrival of the era of large data, the current router architecture is difficult to solve the problem of capacity, efficiency, scalability and power consumption that routers are facing. On the other hand, the network is developing rapidly. The security is facing great challenges. It needs to quickly discover network attack behavior in the router and protect the network data security. In view of the two aspects of network transmission efficiency and data security, this paper presents the features of router SoC (System on Chip) architecture, intra chip communication, interconnection structure diagnosis technology and depth packet detection technology. The key technologies, such as pattern matching technology and function verification, are deeply studied, and some new solutions are put forward to provide reference for the performance of the next generation network router and the improvement of data security.
The main research contents and innovative achievements of the paper include:
1. the intra chip communication mechanism of router SoC is deeply studied, and the shortest path algorithm of Mobius cube is proposed. The algorithm can quickly find a shortest path compared with the algorithm proposed by Cull P. On this basis, all the shortest path lookup algorithms between arbitrary source / destination nodes in the Mobius cube are proposed.
2. based on the 0 /1 type -2 dimension Mobius cube, a kind of router SoC interconnection structure layered routing cross interconnection Mesh structure HRCM suitable for hardware implementation, and the hierarchical routing algorithm suitable for the structure HXY., which has good system performance and extensibility, it is easy to realize the distribution of the router in the IP router. Experimental results show that compared with Xmesh and Mesh, HRCM has more advantages in system throughput, packet loss rate and system average delay.
3. a layered double ring router SoC topology with fault tolerance is proposed. In this structure, the link is divided into two groups of ring networks, one of which has a set of ring nets as the standby ring network. A time division and space division multiplexing routing algorithm is designed for the structure, which separates the control and data, removes the data cache and eliminates the link congestion. Simulation results show that this The structure can effectively avoid congestion, deadlock and starvation, and ensure that the bandwidth is fully utilized.
4. a fast conditional diagnosis algorithm for HRCM under the PMC model is proposed. The whole HRCM network is traversed through the breadth first search. In the ergodic process, the nodes in the HRCM are divided into several sets through the diagnosis between adjacent nodes, and then the fault set and no reason are identified by the relationship between the sets and the number of elements in the set. For the obstacle set, the time complexity of the algorithm is O (N2) for the HRCM network of N*N. This algorithm is also effectively extended to the hypercube, which is used to diagnose the router system composed of multiple routers.
5. for network security, a pattern matching algorithm for depth packet detection system is proposed, which is based on distributed storage based regular expression parallel matching algorithm REPMBDS. experiment. It shows that the algorithm can improve at least 5 times more than the existing serial matching algorithm in processing time, and can effectively deal with high speed and large capacity Intern. Et real-time detection of network intrusion.
6. the function simulation and verification platform of router SoC is designed based on NetFPGA development board. The platform is configured dynamically by the software module to realize the function simulation and verification of different router SoC systems. The HRCM router SoC system of 4*4 is designed and simulated. The routing based on the HRCM interconnection structure on the verification platform is carried out. The device SoC is verified, and the deep packet inspection system is embedded into the SoC structure of the router to perform its function and performance verification.
【學(xué)位授予單位】:西安電子科技大學(xué)
【學(xué)位級(jí)別】:博士
【學(xué)位授予年份】:2014
【分類號(hào)】:TP393.05;TN47
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