本文關(guān)鍵詞： 向量網(wǎng) 向量地址 硬件交換機(jī) NetFPGA 傳輸面　出處：《北京交通大學(xué)》2017年碩士論文　論文類(lèi)型：學(xué)位論文

【摘要】：隨著互聯(lián)網(wǎng)技術(shù)的發(fā)展和網(wǎng)絡(luò)用戶(hù)的大規(guī)模增加,現(xiàn)有網(wǎng)絡(luò)體系在資源控制、QoS、網(wǎng)絡(luò)安全等方面難以滿(mǎn)足網(wǎng)絡(luò)用戶(hù)的應(yīng)用需求,這使得對(duì)新型網(wǎng)絡(luò)體系架構(gòu)的研究成為人們關(guān)注的重要課題。向量網(wǎng)是一種新型網(wǎng)絡(luò)體系架構(gòu),它以向量地址和向量交換為基礎(chǔ),實(shí)現(xiàn)了交換節(jié)點(diǎn)簡(jiǎn)單、輕量向量連接、保證QoS、內(nèi)在可信、向量地址無(wú)限可擴(kuò)展等優(yōu)勢(shì),并通過(guò)將控制面和傳輸面分離開(kāi)來(lái),減少傳輸面路由信息收集、更新、維護(hù)等工作,提高了數(shù)據(jù)轉(zhuǎn)發(fā)的能力。本論文設(shè)計(jì)的向量網(wǎng)硬件交換機(jī)的主要功能是解析向量地址,轉(zhuǎn)發(fā)數(shù)據(jù)包;支持部分向量網(wǎng)信令,處理少量控制面信息。該硬件交換機(jī)的數(shù)據(jù)處理過(guò)程快,資源利用率高。本文根據(jù)向量網(wǎng)理論體系,具體做了如下的設(shè)計(jì)和實(shí)現(xiàn):1.提出一種向量網(wǎng)硬件交換機(jī)功能的改進(jìn)設(shè)計(jì)方案,實(shí)現(xiàn)多級(jí)別數(shù)據(jù)包緩存處理及相關(guān)調(diào)度算法,多級(jí)別數(shù)據(jù)包解析轉(zhuǎn)發(fā)及相關(guān)調(diào)度算法,使向量交換機(jī)可以支持多級(jí)別QoS機(jī)制;2.在ISE環(huán)境,用Verilog語(yǔ)言實(shí)現(xiàn)了一種向量網(wǎng)硬件交換機(jī),包括數(shù)據(jù)包格式的預(yù)處理模塊,數(shù)據(jù)轉(zhuǎn)發(fā)處理模塊,信令支持模塊,輸出控制模塊等,并實(shí)驗(yàn)測(cè)試了相應(yīng)功能;3.在NetFPGA開(kāi)發(fā)板上驗(yàn)證了各個(gè)模塊功能,結(jié)果表明可以滿(mǎn)足向Xilinx Spartan-3A系統(tǒng)XC3S1400A芯片移植的要求。通過(guò)對(duì)向量網(wǎng)硬件交換機(jī)的設(shè)計(jì)和實(shí)現(xiàn),并移植于低成本芯片,達(dá)到低成本實(shí)現(xiàn)1Gbps轉(zhuǎn)發(fā)速率的目的,為向量網(wǎng)的進(jìn)一步部署和應(yīng)用打下基礎(chǔ)。
[Abstract]:With the development of Internet technology and the large-scale increase of network users, the existing network system is difficult to meet the application needs of network users in the aspects of resource control, QoS, network security, etc. This makes the research of new network architecture become an important issue. Vector network is a new network architecture, which is based on vector address and vector switching, and realizes simple switching node and light vector connection. QoS is guaranteed to be inherently credible and vector addresses are infinitely scalable. By separating the control surface from the transmission surface, the routing information collection, updating and maintenance of the transport surface are reduced. The main function of the vector network hardware switch designed in this paper is to resolve the vector address, forward the data packet, support the partial vector network signaling, the main function of this paper is to resolve the vector address, forward the data packet, support the partial vector network signaling, A small amount of control surface information is processed. The data processing process of the hardware switch is fast and the utilization rate of resources is high. In this paper, according to the theory system of vector network, This paper introduces the following design and implementation: 1. An improved design scheme of vector network hardware switch function is proposed, which realizes multi-level packet cache processing and related scheduling algorithm, multi-level packet parsing and forwarding algorithm, and related scheduling algorithm. In the ISE environment, a vector network hardware switch is implemented by using Verilog language, which includes preprocessing module of data packet format, data forwarding processing module, signaling support module, etc. The function of each module is verified on the NetFPGA development board. The result shows that it can meet the requirement of transplanting to the XC3S1400A chip of Xilinx Spartan-3A system. Through the design and implementation of the vector network hardware switch, the output control module and the corresponding function are tested and tested. It is transplanted to low cost chip to achieve the goal of 1Gbps forwarding rate at low cost, which lays the foundation for the further deployment and application of vector network.
【學(xué)位授予單位】：北京交通大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類(lèi)號(hào)】：TP393.02

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