【摘要】：CCD圖像在其獲取過程中由于多種因素的影響會引入一定噪聲，這將給后續(xù)的圖像處理工作帶來一定不便，，因此，對其進行降噪處理則顯得非常重要。 傳統(tǒng)的硬件處理方法如DSP和ASIC等在不同程度上具有一定的缺點，對于遙感圖像的處理并不能達到理想的效果。專用指令集處理器（ASIP）的出現(xiàn)為解決上述問題提供了一種新的手段，其既具有速度快的優(yōu)勢又具有一定的可編程特性，因此對于本文中遙感大幅圖像的并行處理具有良好的適用性。 本文依托某實際項目，具體做了以下三個方面工作： 首先，結合實際需要設計了本文所用的小波處理算法，并重點介紹了本算法在實際應用中的并行使用方法。 其次，設計并實現(xiàn)了一個集成化可編程遙感圖像并行降噪處理機。此系統(tǒng)以FPGA為載體，采用基于ASIP的SIMD結構并行陣列處理方式實現(xiàn)大幅圖像的分塊實時降噪。整個并行處理機主要由ASIP并行處理電路和數(shù)據(jù)分發(fā)與合成電路構成。其可在單片F(xiàn)PGA中集成132個處理內(nèi)核，集成度高。與傳統(tǒng)的SIMD并行處理機不同，此系統(tǒng)中ASIP陣列內(nèi)部設計有保護性功能單元，使得系統(tǒng)中每個ASIP處理單元具有了一定的指令自主執(zhí)行能力。 最后，通過對上述降噪處理機的結構進行分析，結合實際應用場景，設計了參數(shù)配置模塊，以便于地面站對其進行工作狀態(tài)控制和處理參數(shù)調(diào)整。此外，我們還對運算電路進行了優(yōu)化，使得處理速度也有一定程度的提高。 經(jīng)過驗證，該處理機各項性能及降噪效果達到指標要求。結果表明我們設計的并行降噪處理機是正確有效的。
[Abstract]:In the process of CCD image acquisition, a certain noise will be introduced due to the influence of many factors, which will bring some inconvenience to the subsequent image processing, so it is very important to reduce the noise. The traditional hardware processing methods, such as DSP and ASIC, have some shortcomings in different degrees, and the processing of remote sensing images can not achieve the desired results. The emergence of special instruction set processor (ASIP) provides a new method to solve the above problems. Therefore, it has good applicability for parallel processing of remote sensing large scale images in this paper. Based on a practical project, this paper has done the following three aspects: firstly, the wavelet processing algorithm used in this paper is designed according to the actual needs, and the parallel application method of this algorithm in practical application is introduced. Secondly, an integrated programmable remote sensing image parallel de-noising processor is designed and implemented. The system uses FPGA as carrier and uses SIMD structure parallel array processing method based on ASIP to realize real time noise reduction of large scale image. The whole parallel processor is mainly composed of ASIP parallel processing circuit and data distribution and composite circuit. It can integrate 132 processing kernels in a single chip FPGA with high integration. Different from the traditional SIMD parallel processor, the ASIP array in this system is designed with protective function units, which enables each ASIP processing unit in the system to have the ability to execute instructions autonomously. Finally, by analyzing the structure of the noise reduction processor and combining with the practical application scene, a parameter configuration module is designed to facilitate the ground station to control the working state and adjust the processing parameters. In addition, the operation circuit is optimized to improve the processing speed to a certain extent. It has been proved that the performance and noise reduction effect of the processor meet the requirements. The results show that the parallel noise reduction processor designed by us is correct and effective.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TP751

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