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  本文關(guān)鍵詞： 數(shù)字化 JPEG壓縮 圖像傳輸 FPGA　出處：《大連理工大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：目前普遍使用的網(wǎng)絡(luò)視頻相機(jī),由于數(shù)據(jù)傳輸能力的限制,很難做到高清級。因此圖像的前端壓縮的需求越來越大,本文根據(jù)課題要求設(shè)計了圖像數(shù)字壓縮網(wǎng)絡(luò)相機(jī)。 方案采用了JPEG壓縮標(biāo)準(zhǔn)和UDP通信協(xié)議,主要的硬件模塊由前端圖像采集模塊、圖像模數(shù)轉(zhuǎn)換模塊、圖像壓縮模塊、圖像網(wǎng)絡(luò)傳輸模塊和圖像接收顯示模塊組成。其中主控制器本文采用了接口靈活、節(jié)約開發(fā)成本的XC3S50AN這一款FPGA芯片,圖像采集模塊采用了CCD傳感器,將采集的原始圖像數(shù)據(jù)傳輸?shù)綀D像模數(shù)轉(zhuǎn)換模塊SAA7111芯片,實(shí)現(xiàn)圖像信號的數(shù)字化,再由圖像壓縮模塊ZR36060完成JPEG壓縮并經(jīng)由FPGA傳輸?shù)綀D像網(wǎng)絡(luò)傳輸芯片W5300,上位機(jī)模塊則用來接收W5300的數(shù)據(jù)進(jìn)行解碼、存儲和顯示。 系統(tǒng)的軟件部分主要是各模塊驅(qū)動設(shè)計、讀寫控制設(shè)計和上位機(jī)顯示程序。各模塊驅(qū)動和讀寫控制設(shè)計是采用Verilog HDL語言編寫的,由FPGA根據(jù)各模塊時序圖進(jìn)行配置,使下位機(jī)各模塊能正常的工作。其中SAA7111模塊是FPGA通過IIC總線對其進(jìn)行寄存器配置；ZR36060模塊則是設(shè)計了一個IP核來加載配置參數(shù),其同步時鐘信號由SAA7111提供；FPGA作為ZR36060和W5300之間的數(shù)據(jù)緩存；W5300則只需對其接口和網(wǎng)絡(luò)參數(shù)進(jìn)行配置以及收發(fā)TX/RX存儲器大小分配。上位機(jī)部分則是采用MFC界面,通過C++編程實(shí)現(xiàn)圖像的解碼、顯示和保存等功能。 實(shí)驗(yàn)結(jié)果顯示,該系統(tǒng)下位機(jī)能夠完成對圖像的采集、數(shù)字化、壓縮和網(wǎng)絡(luò)傳輸,上位機(jī)能夠清晰的顯示圖像。本文所用傳感器規(guī)格為500×582像素,單幀圖像數(shù)據(jù)量582Kbyte,經(jīng)ZR36060壓縮之后圖像大小為29Kbyte,很好的實(shí)現(xiàn)了圖像數(shù)據(jù)壓縮,壓縮比為20：1。
[Abstract]:Because of the limitation of the data transmission ability, it is difficult to achieve high definition level for the network video camera which is widely used at present. Therefore, the demand for the front end compression of the image is increasing. This paper designs the image digital compression network camera according to the requirements of the subject. The scheme adopts JPEG compression standard and UDP communication protocol. The main hardware modules are front-end image acquisition module, image A / D conversion module, image compression module. Image network transmission module and image receiving and displaying module. The main controller adopts XC3S50AN chip, which has flexible interface and saves development cost. CCD sensor is used in image acquisition module. The original image data is transmitted to the image A / D conversion module SAA7111 chip to realize the digitization of the image signal. Then the image compression module ZR36060 completes the JPEG compression and transmits to the image network transmission chip W5300 via FPGA. The upper computer module is used to receive the W5300 data for decoding, storage and display. The software part of the system is mainly about the design of each module driver, read / write control design and host computer display program. Each module driver and read / write control design is written in Verilog HDL language, which is configured by FPGA according to the timing diagram of each module. The SAA7111 module is the FPGA to configure its register through the IIC bus ZR36060 module is designed an IP core to load configuration parameters. The synchronous clock signal is provided by SAA7111 as the data buffer between ZR36060 and W5300. The W5300 only needs to configure its interface and network parameters and allocate the size of TX/RX memory, while the upper computer uses MFC interface. The function of image decoding, displaying and saving is realized by C programming. The experimental results show that the system can collect, digitize, compress and transmit the image clearly, and the upper computer can display the image clearly. The sensor specification is 500 脳 582 pixels. The single frame image data volume is 582 Kbyte.After ZR36060 compression, the image size is 29Kbyte. the image data compression is very good, the compression ratio is 20: 1.
【學(xué)位授予單位】：大連理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TB852.1

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本文編號：1555792