高速TDM-PON系統(tǒng)ONU方案設(shè)計(jì)與實(shí)現(xiàn)
發(fā)布時(shí)間：2019-06-05 23:59
【摘要】：10G EPON已成為業(yè)界公認(rèn)的目前光接入網(wǎng)提速的主流解決方案之一,要深入的研究10G EPON系統(tǒng)實(shí)際應(yīng)用所面臨的各類(lèi)問(wèn)題,如深度業(yè)務(wù)識(shí)別、QoS保證等需要基于一個(gè)靈活的、可編程設(shè)計(jì)實(shí)現(xiàn)以驗(yàn)證新機(jī)制新功能的10GEPON系統(tǒng)平臺(tái),而目前商用10GEPON ASIC芯片功能固化,難以滿足創(chuàng)新研究的特殊要求,所以設(shè)計(jì)一款基于FPGA、擁有自主知識(shí)產(chǎn)權(quán)的10GEPON系統(tǒng)很有必要。此外,隨著未來(lái)各種網(wǎng)絡(luò)業(yè)務(wù)的發(fā)展,對(duì)接入網(wǎng)絡(luò)帶寬需求勢(shì)必急劇增加,覆蓋范圍也將進(jìn)一步擴(kuò)大,為滿足這些新需求,將單波長(zhǎng)速率從10Gbps提升到4OGbps.傳輸距離擴(kuò)展到40km的下一代PON系統(tǒng)成為光接入網(wǎng)發(fā)展演進(jìn)的必然趨勢(shì)之一。本文圍繞實(shí)現(xiàn)基于FPGA的10G EPON系統(tǒng)平臺(tái)和滿足下一代PON大容量、長(zhǎng)距離、廣覆蓋的目標(biāo)要求,進(jìn)行了兩款PON系統(tǒng)ONU設(shè)備的設(shè)計(jì)開(kāi)發(fā),具體開(kāi)展的工作總結(jié)如下： (1)10G EPON ONU電路方案設(shè)計(jì)、實(shí)現(xiàn) ①參與完成10G EPON ONU總體設(shè)計(jì)方案：根據(jù)需求分析,確立了符合IEEE802.3av國(guó)際標(biāo)準(zhǔn),支持10G上聯(lián)接口、FE/GE用戶接口等技術(shù)指標(biāo),并進(jìn)行模塊設(shè)計(jì)。 ②完成電路原理圖設(shè)計(jì),主要包括PON側(cè)10G接口、FPGA、 SGMII到GMII的接口轉(zhuǎn)換、嵌入式系統(tǒng)等模塊電路設(shè)計(jì)。 ③完成10G EPON ONU單板功能調(diào)試及系統(tǒng)聯(lián)合測(cè)試,主要包括PON側(cè)XSBI/SFP+、用戶側(cè)FE/GE接口、SGMII to GMII轉(zhuǎn)換等調(diào)試及與商用OLT互通、系統(tǒng)聯(lián)合測(cè)試,測(cè)試結(jié)果表明10G EPON ONU方案符合設(shè)計(jì)要求。(2)40Gbps TDM-PON ONU電路方案設(shè)計(jì)、實(shí)現(xiàn) ①參與完成以下行40Gbps,上行10Gbps、分支比1：32,最長(zhǎng)傳輸距離和最大距離差40km為核心目標(biāo)的TDM-PON ONU總體方案及內(nèi)部幀過(guò)濾復(fù)用、40G解幀、相干接收、控制等功能模塊設(shè)計(jì)。 ②完成電路原理圖設(shè)計(jì),主要包括用戶側(cè)10G接口、PON側(cè)40G光模塊、FP(GA、時(shí)鐘、高速XAUI、SFI-5、XFI等的設(shè)計(jì)。 ③參與電路PCB設(shè)計(jì),制定PCB疊層結(jié)構(gòu)、高速接口布線等要求。最終實(shí)現(xiàn)的40bps TDM-PON ONU主板多達(dá)18層,近24000pins,子板10層,約3000pins。 ④完成單板功能模塊的調(diào)試,主要包括用戶側(cè)接口調(diào)試、PON側(cè)接口調(diào)試、上行鏈路及下行鏈路調(diào)試等,調(diào)試結(jié)果驗(yàn)證了方案設(shè)計(jì)的合理性和可行性。
[Abstract]:10G EPON has become one of the mainstream solutions to increase the speed of optical access network. In order to deeply study all kinds of problems faced by the practical application of 10G EPON system, such as deep service identification, QoS guarantee and so on, it needs to be based on a flexible. Programmable design and implementation of 10GEPON system platform to verify the new mechanism and new functions, but the current commercial 10GEPON ASIC chip function solidified, it is difficult to meet the special requirements of innovative research, so the design is based on FPGA, It is necessary to have a 10GEPON system with independent intellectual property rights. In addition, with the development of various network services in the future, the demand for access network bandwidth is bound to increase sharply, and the coverage will also be further expanded. In order to meet these new requirements, the single wavelength rate will be increased from 10Gbps to 4OGbPs. The next generation PON system whose transmission distance extends to 40km has become one of the inevitable trends in the development and evolution of optical access network. In this paper, the design and development of two PON system ONU devices are carried out to realize the 10G EPON system platform based on FPGA and to meet the requirements of large capacity, long distance and wide coverage of the next generation PON. The specific work is summarized as follows: (1) 10G EPON ONU circuit scheme design, 1 participate in the completion of 10G EPON ONU overall design scheme: according to the requirement analysis, established in accordance with IEEE802.3av international standards, support 10G uplink interface, FE/GE user interface and other technical indicators, and module design. 2 complete the circuit schematic design, including PON side 10G interface, FPGA, SGMII to GMII interface conversion, embedded system and other module circuit design. (3) complete 10G EPON ONU single board function debugging and system joint test, including PON side XSBI/SFP, user side FE/GE interface, SGMII to GMII conversion debugging, interworking with commercial OLT, system joint test. The test results show that the 10G EPON ONU scheme meets the design requirements. (2) 40Gbps TDM-PON ONU circuit scheme design, 1 participate in the completion of the following lines 40Gbps, uplink 10Gbps, branch ratio 1 鈮，
本文編號(hào)：2493911
[Abstract]:10G EPON has become one of the mainstream solutions to increase the speed of optical access network. In order to deeply study all kinds of problems faced by the practical application of 10G EPON system, such as deep service identification, QoS guarantee and so on, it needs to be based on a flexible. Programmable design and implementation of 10GEPON system platform to verify the new mechanism and new functions, but the current commercial 10GEPON ASIC chip function solidified, it is difficult to meet the special requirements of innovative research, so the design is based on FPGA, It is necessary to have a 10GEPON system with independent intellectual property rights. In addition, with the development of various network services in the future, the demand for access network bandwidth is bound to increase sharply, and the coverage will also be further expanded. In order to meet these new requirements, the single wavelength rate will be increased from 10Gbps to 4OGbPs. The next generation PON system whose transmission distance extends to 40km has become one of the inevitable trends in the development and evolution of optical access network. In this paper, the design and development of two PON system ONU devices are carried out to realize the 10G EPON system platform based on FPGA and to meet the requirements of large capacity, long distance and wide coverage of the next generation PON. The specific work is summarized as follows: (1) 10G EPON ONU circuit scheme design, 1 participate in the completion of 10G EPON ONU overall design scheme: according to the requirement analysis, established in accordance with IEEE802.3av international standards, support 10G uplink interface, FE/GE user interface and other technical indicators, and module design. 2 complete the circuit schematic design, including PON side 10G interface, FPGA, SGMII to GMII interface conversion, embedded system and other module circuit design. (3) complete 10G EPON ONU single board function debugging and system joint test, including PON side XSBI/SFP, user side FE/GE interface, SGMII to GMII conversion debugging, interworking with commercial OLT, system joint test. The test results show that the 10G EPON ONU scheme meets the design requirements. (2) 40Gbps TDM-PON ONU circuit scheme design, 1 participate in the completion of the following lines 40Gbps, uplink 10Gbps, branch ratio 1 鈮，
本文編號(hào)：2493911
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