【摘要】：隨著信息技術(shù)的發(fā)展與進(jìn)步,數(shù)字視頻通信也成為該領(lǐng)域研究的熱點(diǎn)話題之一。AVS標(biāo)準(zhǔn)是中國(guó)數(shù)字音視頻編解碼技術(shù)標(biāo)準(zhǔn)工作組制定的具有自主知識(shí)產(chǎn)權(quán)的數(shù)字音視頻編碼標(biāo)準(zhǔn),性能與H.264標(biāo)準(zhǔn)相當(dāng)。AVS標(biāo)準(zhǔn)已成為我國(guó)高清數(shù)字電視、網(wǎng)絡(luò)電視、視頻通信等重要音視頻應(yīng)用的基礎(chǔ)標(biāo)準(zhǔn)。 AVS標(biāo)準(zhǔn)采用了一系列的先進(jìn)技術(shù),有效地提高了視頻編碼效率,實(shí)時(shí)編碼的數(shù)據(jù)吞吐率很高。FPGA擁有豐富的寄存器資源和邏輯資源,其高性能和靈活性能夠滿(mǎn)足高速?gòu)?fù)雜電子線路設(shè)計(jì)的需求。 本研究提出一種新型架構(gòu)——片內(nèi)云架構(gòu),并在此架構(gòu)下完成了AVS編碼器Ⅰ幀的優(yōu)化及實(shí)現(xiàn)。設(shè)計(jì)了片內(nèi)只寫(xiě)總線(BoW)以及基于其自身特點(diǎn)的消息訪問(wèn)機(jī)制。片內(nèi)只寫(xiě)總線網(wǎng)絡(luò)拓?fù)浣Y(jié)構(gòu)簡(jiǎn)單,有利于原子構(gòu)件的高度并行和流水處理,適用于處理數(shù)據(jù)量大、復(fù)雜度高的視頻編碼算法。將AVS算法模塊封裝成基于消息訪問(wèn)的原子構(gòu)件,通過(guò)統(tǒng)一節(jié)點(diǎn)接口連接到總線上。 根據(jù)AVS編碼算法的特點(diǎn),本文在FPGA上設(shè)計(jì)實(shí)現(xiàn)了AVS編碼器Ⅰ幀算法。將AVS編碼Ⅰ幀的實(shí)現(xiàn)分為5個(gè)功能模塊,將各模塊封裝成原子構(gòu)件,包括圖像采集原子構(gòu)件、亮度預(yù)測(cè)變換原子構(gòu)件、亮度編碼原子構(gòu)件和、色度預(yù)測(cè)變換原子構(gòu)件和色度編碼原子構(gòu)件。綜合考慮Ⅰ幀算法的特點(diǎn)和原子構(gòu)件粒度的劃分原則,取代傳統(tǒng)以16×16宏塊為基本單元的數(shù)據(jù)塊模式,將其再一步細(xì)化為8×8塊的模式。這種更精細(xì)的粒度劃分有效地減少了原子構(gòu)件與流程引擎間通信的時(shí)間,節(jié)省了硬件資源,提高了編碼效率。 為提高數(shù)據(jù)處理的速度,實(shí)現(xiàn)視頻的實(shí)時(shí)編碼,各模塊采用高度并行算法和流水線設(shè)計(jì)方法。利用該架構(gòu)的本身特點(diǎn),本文采用重復(fù)部署多個(gè)原子構(gòu)件的方法,利用多個(gè)流程調(diào)用的并行執(zhí)行方式,又進(jìn)一步提高了編碼效率,實(shí)現(xiàn)了對(duì)高分辨率圖像的實(shí)時(shí)編碼。通過(guò)ISE與ModelSim綜合仿真,其最高時(shí)鐘頻率可達(dá)130MHz,可在Virtex-5平臺(tái)上實(shí)現(xiàn)D1分辨率Ⅰ幀圖像的實(shí)時(shí)編碼。
[Abstract]:With the development and progress of information technology, digital video communication has become one of the hot topics in this field. AVS standard is a digital audio and video coding standard with independent intellectual property rights developed by China Digital Audio Video coding and Decoding Technical Standard working Group. The performance is equivalent to H.264 standard. AVS standard has become the basic standard of high definition digital TV, network television, video communication and other important audio and video applications. AVS standard has adopted a series of advanced technology. The efficiency of video coding is improved effectively. The data throughput of real-time coding is very high. FPGA has abundant register and logic resources, and its high performance and flexibility can meet the needs of high-speed and complex electronic circuit design. In this paper, we propose a new architecture, the in-chip cloud architecture, and optimize and implement the frame I of AVS encoder. A write-only bus (BoW) and a message access mechanism based on its own characteristics are designed. The on-chip write-only network topology is simple, which is conducive to the highly parallel and pipelined processing of atomic components. It is suitable for video coding algorithms with large data volume and high complexity. The AVS algorithm module is encapsulated as an atomic component based on message access and connected to the bus through a unified node interface. According to the characteristics of AVS coding algorithm, this paper designs and implements the frame I algorithm of AVS encoder on FPGA. The realization of AVS coding frame I is divided into five functional modules. Each module is encapsulated into atomic components, including image acquisition atomic component, brightness prediction transformation atomic component, luminance coding atomic component and, Chromaticity prediction transformation atomic component and chrominance coded atomic component. Considering the characteristics of frame I algorithm and the partition principle of atomic component granularity, this paper replaces the traditional data block mode with 16 脳 16 macroblock as the basic unit, and further refines it to 8 脳 8 block mode. The finer granularity partition reduces the communication time between the atomic component and the process engine, saves the hardware resources and improves the coding efficiency. In order to improve the speed of data processing and realize real-time video coding, each module adopts highly parallel algorithm and pipeline design method. Taking advantage of the characteristics of the architecture, this paper adopts the method of repeatedly deploying multiple atomic components, utilizes the parallel execution mode of multiple process calls, and further improves the coding efficiency and realizes the real-time coding of high-resolution images. Through the simulation of ISE and ModelSim, the highest clock frequency can be up to 130 MHz, and the D1 resolution I frame image can be encoded in real time on Virtex-5 platform.
【學(xué)位授予單位】：太原理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類(lèi)號(hào)】：TN919.81

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