【摘要】：AVS是我國自主知識產(chǎn)權(quán)的音視頻編解碼標(biāo)準(zhǔn),由AVS工作組制定。AVS-S是在AVS的基礎(chǔ)上發(fā)展起來的,主要針對安防監(jiān)控領(lǐng)域的數(shù)字視頻編解碼標(biāo)準(zhǔn),可以滿足遠(yuǎn)程視頻監(jiān)控的特殊要求。該標(biāo)準(zhǔn)的提出,不僅推動了我國安防產(chǎn)業(yè)的發(fā)展,也為我國解決了很多專利壁壘問題,節(jié)約了專利費用。本文首先對AVS-S標(biāo)準(zhǔn)進(jìn)行了深入研究,然后分析和優(yōu)化了該標(biāo)準(zhǔn)中變換、量化和熵編碼模塊所采用的算法,最后對這三個模塊進(jìn)行了硬件設(shè)計和優(yōu)化。根據(jù)ICT變換的特點,采用1-DICT變換和8×8的轉(zhuǎn)置矩陣實現(xiàn)2-DICT變換；對傳統(tǒng)的蝶形算法進(jìn)行了優(yōu)化,變換后的系數(shù)無需重新排序,降低了變換的復(fù)雜度。量化模塊中,修改了求解加權(quán)量化矩陣的方法,避免了多余中間變量的存儲,節(jié)省了資源；量化后的系數(shù)直接按Zig-Zag掃描的順序存入緩存,減少了對存儲器的訪問,節(jié)省了編碼時間；量化模塊支持傳統(tǒng)的非加權(quán)量化技術(shù)和質(zhì)量可調(diào)整的加權(quán)量化技術(shù),兩種量化技術(shù)復(fù)用一個縮放量化模塊,節(jié)約了資源。在熵編碼模塊中,根據(jù)run、level和trans_coeffcient的大小關(guān)系,對碼表進(jìn)行了壓縮,降低了查表的復(fù)雜度。本文采用并行流水線的方式,加快了編碼速度。本文采用Verilog HDL語言完成AVS-S編碼器中變換、量化和熵編碼模塊的RTL級電路,采用Synopsys的VCS進(jìn)行功能驗證,采用AVS-S標(biāo)準(zhǔn)參考軟件SM2_0.4-v3建立參考模型,將VCS的仿真結(jié)果與參考模型的結(jié)果進(jìn)行對比來驗證本設(shè)計的正確性。在Synopsys的Design Compiler綜合工具上進(jìn)行邏輯綜合,結(jié)果顯示,該設(shè)計滿足時序要求。最后用Formality形式驗證工具對設(shè)計進(jìn)行了形式驗證。
[Abstract]:AVS is the standard of audio and video coding and decoding of independent intellectual property rights in China. It was developed by the AVS working group on the basis of AVS, and is mainly aimed at the digital video coding and decoding standard in the field of security and surveillance. It can meet the special requirements of remote video surveillance. The proposal of this standard not only promotes the development of China's security industry, but also solves a lot of patent barriers and saves patent expenses. In this paper, the AVS-S standard is studied deeply, then the algorithms used in the transform, quantization and entropy coding modules are analyzed and optimized. Finally, the hardware design and optimization of the three modules are given. According to the characteristics of ICT transform, 1-DICT transform and 8 脳 8 transpose matrix are used to realize 2-DICT transform, the traditional butterfly algorithm is optimized, the coefficients after transformation need not be reordered, and the complexity of transformation is reduced. In the quantization module, the method of solving the weighted quantization matrix is modified to avoid the storage of superfluous intermediate variables and save resources, and the quantized coefficients are stored directly in the order of Zig-Zag scanning, and the access to memory is reduced. The quantization module supports the traditional unweighted quantization technique and the quality adjustable weighted quantization technology. The two quantization techniques reuse a scalable quantization module and save resources. In the entropy coding module, the code table is compressed according to the relation between running-level and trans_coeffcient, which reduces the complexity of searching table. In this paper, parallel pipelining is used to speed up the coding speed. In this paper, Verilog HDL language is used to complete the RTL level circuit of the AVS-S encoder, and the Synopsys VCS is used to verify the function. The AVS-S standard reference software SM2_0.4-v3 is used to build the reference model. The simulation results of VCS and the results of reference model are compared to verify the correctness of the design. Logic synthesis is carried out on the Design Compiler synthesis tool of Synopsys. The result shows that the design meets the requirement of time sequence. Finally, Formality formal verification tool is used to verify the design.
【學(xué)位授予單位】：山東大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN919.81

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本文編號：2141031