本文選題：JTAG + MCU　； 參考：《西安科技大學(xué)》2013年碩士論文

【摘要】：嵌入式微控制器（MCU）片內(nèi)集成了CPU、通信接口、模數(shù)和數(shù)模外設(shè)、內(nèi)存等部件，已逐漸發(fā)展成為片上系統(tǒng)（SOC），簡化了應(yīng)用系統(tǒng)設(shè)計(jì)，使計(jì)算機(jī)技術(shù)從大型的通用型數(shù)值計(jì)算領(lǐng)域進(jìn)入到小型化、智能化領(lǐng)域，擴(kuò)大了計(jì)算機(jī)技術(shù)的應(yīng)用范圍。 在嵌入式系統(tǒng)開發(fā)過程中，系統(tǒng)軟硬件調(diào)試是嵌入式系統(tǒng)開發(fā)的重要環(huán)節(jié)，一個(gè)高效強(qiáng)大的調(diào)試系統(tǒng)可以大大縮短系統(tǒng)的開發(fā)周期，增強(qiáng)產(chǎn)品的競爭力。在嵌入式應(yīng)用系統(tǒng)中，如何利用可控的調(diào)試手段實(shí)現(xiàn)對芯片內(nèi)部測試與軟件運(yùn)行狀態(tài)監(jiān)控一直是微控器調(diào)試技術(shù)的一個(gè)難點(diǎn)。目前基于JTAG協(xié)議標(biāo)準(zhǔn)（IEEE Standard1149.1-TESTAccess Portand Boundary-Scan Architecture）的在線調(diào)試技術(shù)仍是嵌入式應(yīng)用系統(tǒng)最有效的調(diào)試方式。 基于JTAG標(biāo)準(zhǔn)的調(diào)試技術(shù)，就是在MCU芯片內(nèi)設(shè)計(jì)符合JTAG協(xié)議標(biāo)準(zhǔn)的內(nèi)嵌調(diào)試結(jié)構(gòu)和模塊，實(shí)現(xiàn)對目標(biāo)CPU啟�？刂疲O(shè)置程序計(jì)數(shù)器，讀/寫內(nèi)存，塊讀/寫，設(shè)置硬件斷點(diǎn)以及對片內(nèi)FLASH在線擦除編程等操作，方便用戶對MCU應(yīng)用系統(tǒng)的在線開發(fā)調(diào)試。 MCU內(nèi)嵌JTAG接口后，MCU程序的下載以及片上存儲器的讀寫就可以通過JTAG接口進(jìn)行。但一般實(shí)現(xiàn)的JTAG接口安全性較差，只要符合JTAG標(biāo)準(zhǔn)的控制器就可以將程序代碼讀出。本文結(jié)合一款16位低功耗微控制器（MCU）的設(shè)計(jì)，提出了一種JTAG調(diào)試功能模塊的結(jié)構(gòu)設(shè)計(jì)，在芯片上集成了JTAG熔絲，應(yīng)用開發(fā)工程師在軟件開發(fā)結(jié)束后可以通過熔斷JTAG熔絲的方法，使得非授權(quán)用戶無法讀取片內(nèi)存儲器的內(nèi)容，，保護(hù)了自身的知識產(chǎn)權(quán)。同時(shí)對部分JTAG引腳采用多功能復(fù)用設(shè)計(jì)，節(jié)省的引腳資源可用于外設(shè)以豐富產(chǎn)品的功能，或是縮小封裝體積，實(shí)現(xiàn)小型化，降低使用成本。在此基礎(chǔ)上，采用0.25um CMOS工藝，完成了芯片的電路和版圖設(shè)計(jì)，并進(jìn)行了流片和測試。
[Abstract]:Embedded microcontroller (MCU) integrated with CPU, communication interface, analog and digital peripheral, memory and so on, has gradually developed into a system on a chip, which simplifies the design of application system. In the process of developing embedded system, the computer technology has entered the field of miniaturization and intelligentization from the field of large-scale general numerical calculation, and the application of computer technology has been expanded. System hardware and software debugging is an important part of embedded system development. An efficient and powerful debugging system can greatly shorten the development cycle of the system and enhance the competitiveness of the products. In the embedded application system, how to use controllable debugging means to realize the chip internal testing and software running state monitoring has been a difficult point in the microcontroller debugging technology. At present, the on-line debugging technology based on JTAG protocol standard, IEEE Standard 1149.1-TESTAccess Port and Boundary ary-Scan Architecture, is still the most effective debugging method for embedded application system. The debugging technology based on JTAG standard is to design embedded debugging structure and module in MCU chip, which conforms to JTAG protocol standard. To achieve the target CPU start and stop control, set up program counters, read / write memory, block read / write, set hardware breakpoints and on-chip flash online erasure programming operations, etc. It is convenient for users to develop and debug MCU application system on line. The download of MCU program and the reading and writing of on-chip memory can be carried out through JTAG interface after embedded JTAG interface in MCU. However, the JTAG interface implemented in general is of poor security, so long as the controller can read the program code according to the JTAG standard. Based on the design of a 16-bit low power microcontroller (MCU), a JTAG debugging function module is designed. The JTAG fuse is integrated on the chip, and the application development engineer can fuse the JTAG fuse after the software development is finished. This prevents unauthorized users from reading the contents of on-chip memory and protects their intellectual property rights. At the same time, some JTAG pins are designed with multifunctional reuse. The saved pin resources can be used to enrich the functions of the products, or to reduce the package size, realize miniaturization and reduce the cost of use. On this basis, the circuit and layout of the chip are designed by using 0.25um CMOS technology, and the chip flow and test are carried out.
【學(xué)位授予單位】：西安科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TN402

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