本文選題：高速數(shù)據(jù)采集 + FMC��； 參考：《電子科技大學》2013年碩士論文

【摘要】：數(shù)據(jù)采集作為通信技術的重要環(huán)節(jié)，在通信技術迅猛發(fā)展的同時，對數(shù)據(jù)采集系統(tǒng)的性能要求越來越高，可以說在高速高精度的前提下，高密度、高集成、可擴展兼容是數(shù)據(jù)采集系統(tǒng)今后的發(fā)展趨勢之一。 本文設計的FMC（FPGA Mezzanine Card）系列采集模塊正是迎合了當今數(shù)據(jù)采集系統(tǒng)的發(fā)展趨勢，以靈活可擴展的方式解決寬帶信號的捕獲、以高度集成的體系結構解決電子系統(tǒng)的嵌入式測試為目標，利用FMC VITA-57標準協(xié)議，在標準有限面積內(nèi)，設計實現(xiàn)了一種具有高集成、高密度、可擴展兼容等特點的高速高精度采集模塊。 FMC系列采集模塊分為FMC5212（雙通道500MSPS/12bits）和FMC4214（雙通道400MSPS/14bits），兩款產(chǎn)品分別采用AD芯片ADS5463和ADS5474，時鐘芯片AD9517-3分別為其提供所需的采樣時鐘來完成AD轉換。模塊的兼容性設計方面，在接口邏輯中設計了識別功能來對FMC身份進行識別與驗證；為了保護模塊設計及其邏輯代碼的知識產(chǎn)權，設計了加密防拷貝模塊來對FMC接口邏輯進行軟件保護；針對高密度、高度集成所導致的模塊溫度高、電源及信號完整性問題，文中通過對系統(tǒng)功耗和溫度，以及串擾與軌道塌陷等問題的詳細分析，完成了高效率的電源設計及系統(tǒng)板級設計，，同時設計了狀態(tài)監(jiān)控模塊對溫度及電源加以實時監(jiān)控。最終對設計結果進行測試與驗證，該采集模塊SNR、SFDR均達到設計指標，而識別加密模塊及狀態(tài)監(jiān)控模塊均得到驗證，滿足測試要求， 論文主要內(nèi)容可分為： FMC系列采集模塊的硬件設計：AD采樣模塊、采樣時鐘模塊、觸發(fā)模塊、加密識別模塊、溫度電壓監(jiān)控模塊、電源模塊等設計。 FMC系列采集模塊接口邏輯的設計：數(shù)據(jù)解串、配置采樣時鐘、加密防拷貝、身份識別、監(jiān)控溫度與電壓等。 對FMC系列FMC5212和FMC4214進行結果測試及功能驗證。
[Abstract]:As an important link of communication technology, data acquisition is becoming more and more demanding for the performance of the data acquisition system while the communication technology is developing rapidly. It can be said that high density, high integration and extensible compatibility are one of the future development trends of data acquisition system in the premise of high speed and high precision.
The FMC (FPGA Mezzanine Card) collection module designed in this paper is to cater to the development trend of today's data acquisition system, to solve the acquisition of broadband signal in a flexible and extensible way, and to solve the embedded test of electronic system with a highly integrated architecture, and use the FMC VITA-57 standard protocol in the limited area of the standard. A high speed and high precision acquisition module with high integration, high density, scalability and compatibility is designed and implemented.
The FMC collection module is divided into FMC5212 (dual channel 500MSPS/12bits) and FMC4214 (dual channel 400MSPS/14bits). The two products use AD chip ADS5463 and ADS5474 respectively. The clock chip AD9517-3 respectively provides the required sampling clock to complete the AD conversion. The module is designed with the recognition function to the F in the interface logic. MC identity is identified and verified. In order to protect the intellectual property of module design and its logical code, an encrypted and anti copy module is designed to protect the software of FMC interface logic. High density, high integration results in high module temperature, power and signal integrity problems, through the system power and temperature, and crosstalk in this paper. With the detailed analysis of the track collapse and other problems, the high efficiency power supply design and the system board level design are completed. At the same time, the state monitoring module is designed to monitor the temperature and the power supply in real time. Finally, the design results are tested and verified. The acquisition module SNR, SFDR all achieve the design index, and the recognition encryption module and the state monitoring module are both. To be verified and meet the test requirements.
The main contents of the paper can be divided into:
The hardware design of FMC series acquisition module: AD sampling module, sampling clock module, trigger module, encryption recognition module, temperature and voltage monitoring module, power module and so on.
Design of interface logic for FMC series acquisition module: Data deserializer, configuration sampling clock, encryption and anti copy, identity recognition, monitoring temperature and voltage, etc.
The result test and functional verification of FMC series FMC5212 and FMC4214 are carried out.

【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP274.2

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