本文選題：橢圓曲線密碼體制 + 點乘�。� 參考：《杭州電子科技大學(xué)》2014年碩士論文

【摘要】：隨著信息安全需求的日益增長，目前普遍采用的1024位RSA算法面臨嚴(yán)重的安全威脅，而ECC（橢圓曲線密碼）算法相比RSA算法在安全性和加解密速率方面具有顯著的優(yōu)勢，為了保障重要經(jīng)濟(jì)領(lǐng)域密碼應(yīng)用的安全，我國國家密碼管理局制定了具有自主知識產(chǎn)權(quán)的ECC國家標(biāo)準(zhǔn)算法（即SM2算法），公布了相關(guān)標(biāo)準(zhǔn)及規(guī)范，并要求相關(guān)行業(yè)采用SM2算法替換RSA算法。同時，針對ECC算法的旁路攻擊技術(shù)也是層出不窮，其中功耗分析攻擊就是利用ECC在加解密過程中泄露的功耗信息進(jìn)行攻擊，這種攻擊方法效率高，威脅性大。因此，ECC國家標(biāo)準(zhǔn)算法如何高速實現(xiàn)及其抗功耗分析攻擊的研究成為當(dāng)前及未來密碼產(chǎn)業(yè)關(guān)注的熱點。 本文針對ECC的應(yīng)用需求，設(shè)計了一款面向SOC設(shè)計的素數(shù)域上ECC加速器IP，結(jié)合ECC算法原理和硬件實現(xiàn)的特點，提出一種安全、高效、易實現(xiàn)的算法方案，用軟件驗證了方案的正確性和可行性后，采用verilog硬件描述語言完成ECC加速器的RTL設(shè)計，并通過詳細(xì)的仿真驗證及邏輯綜合，驗證了加速器的算法正確性、速度以及面積等性能指標(biāo)。除此之外，本文針對加密算法搭建了功耗分析攻擊平臺，為驗證ECC加速器抗功耗分析攻擊的能力奠定了基礎(chǔ)。 本文實現(xiàn)的加速器支持192/256bit多種橢圓曲線的應(yīng)用，支持固定基單基點乘和雙點乘運(yùn)算，其中雙點乘運(yùn)算中提出了從左到右聯(lián)合編碼和Shamir雙點乘相結(jié)合的快速算法。加速器基于SMIC0.13um工藝和200MHz頻率，，256bit素數(shù)域上每秒能完成5000次簽名和1600次驗證。這對于今后高性能的密碼芯片產(chǎn)品研發(fā)有著重要的參考意義。
[Abstract]:With the increasing demand for information security, the widely used 1024 bit RSA algorithm is facing a serious security threat. Compared with the RSA algorithm, the ECC (elliptic curve cryptography) algorithm has significant advantages in terms of security and encryption and decryption rate. In order to ensure the security of cryptographic applications in important economic fields, the State Cryptography Administration of China has formulated the ECC national standard algorithm (SM2 algorithm) with independent intellectual property rights, and published the relevant standards and specifications. And requires the relevant industries to replace the RSA algorithm with the SM2 algorithm. At the same time, the bypass attack technology for ECC algorithm is emerging in endlessly, in which power analysis attack is to use the power information leaked in the process of encryption and decryption of ECC to attack. This attack method is highly efficient and threatening. Therefore, how to implement the ECC national standard algorithm at high speed and how to resist the power analysis attack has become a hot topic in the cryptographic industry at present and in the future. According to the application requirements of ECC, this paper designs a ECC accelerator for SOC design in prime number domain. Combining with the principle of ECC algorithm and the characteristics of hardware implementation, a safe, efficient and easy to implement algorithm scheme is proposed. After the correctness and feasibility of the scheme are verified by software, the RTL design of ECC accelerator is completed by using verilog hardware description language, and the algorithm of the accelerator is verified by detailed simulation and logic synthesis. Speed and area and other performance indicators. In addition, this paper builds a power analysis attack platform for encryption algorithm, which lays a foundation for verifying the ability of ECC accelerator to resist power analysis attack. The accelerator implemented in this paper supports the application of multiple elliptic curves of 192/256bit, and supports the fixed basis single base point multiplication and double point multiplication operations. In the double point multiplication operation, a fast algorithm combining left to right joint coding and Shamir double point multiplication is proposed. The accelerator can complete 5000 signatures and 1600 verifications per second based on the SMIC0.13um process and the 200MHz frequency of 256bit prime number domain. This is of great significance for the future research and development of high-performance cipher chip products.
【學(xué)位授予單位】：杭州電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN918.4

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