本文選題：片上系統(tǒng) + CPU核　； 參考：《西安電子科技大學(xué)》2014年碩士論文

【摘要】：近十年來,由于無線通信設(shè)備市場的強(qiáng)勁增長,使得移動(dòng)通信基帶芯片而受到廣泛關(guān)注。隨著片上系統(tǒng)(System on-chip,SoC)設(shè)計(jì)規(guī)模的增大和復(fù)雜性的增加,驗(yàn)證工作在數(shù)字電路中的地位變得越來越重要。本文基于通信基帶SoC芯片的研發(fā)項(xiàng)目,對系統(tǒng)級驗(yàn)證中平臺的設(shè)計(jì)和優(yōu)化的問題進(jìn)行了深入研究,給出了完整的優(yōu)化解決方案和測試用例的分析。首先,通過介紹系統(tǒng)級驗(yàn)證平臺基本功能和結(jié)構(gòu),具體分析了SystemVerilog驗(yàn)證平臺的工作原理及其組件之間聯(lián)系。在此基礎(chǔ)上,針對現(xiàn)有驗(yàn)證平臺的需求進(jìn)行分析并提出優(yōu)化設(shè)計(jì)目標(biāo)。然后,根據(jù)優(yōu)化目標(biāo)提出具體優(yōu)化設(shè)計(jì)方法,即部分硬件實(shí)體的抽象虛擬化,主要分為兩部分:一方面是CPU(Central Processing Unit)的虛擬化,另一方面是總線功能模型的抽象。通過這兩部分的虛擬模型來替換實(shí)體,簡化設(shè)計(jì)。對于CPU的虛擬化,可以在驗(yàn)證平臺上模擬CPU的行為建立一個(gè)模型cRunner,它能將測試用例的C程序轉(zhuǎn)換成SV程序,直接在仿真器上執(zhí)行。而cRunner與其他模塊通信的總線模型,可采用開放核心協(xié)議(Open Core Protocol,OCP)和通用驗(yàn)證方法學(xué)(Universal Verification Methodology),設(shè)計(jì)一個(gè)總線功能模型OCP_agent,它能實(shí)現(xiàn)從cRunner到NoC的接口協(xié)議轉(zhuǎn)換,從而對寄存器/存儲(chǔ)器的進(jìn)行訪問。優(yōu)化后的驗(yàn)證平臺稱為統(tǒng)一的驗(yàn)證平臺(Unified Testbench,UTB)。在UTB上采用軟硬件協(xié)同仿真策略,實(shí)現(xiàn)了仿真過程的加速和無核心系統(tǒng)下的仿真驗(yàn)證,達(dá)到了預(yù)期的優(yōu)化設(shè)計(jì)目標(biāo)。最后,在原有的驗(yàn)證平臺和優(yōu)化的驗(yàn)證平臺分別進(jìn)行測試用例的仿真,仿真包括系統(tǒng)級仿真和門級仿真。得出的數(shù)據(jù)結(jié)果,進(jìn)行對比分析,實(shí)際物理仿真時(shí)間減少了83.9%。證明優(yōu)化的驗(yàn)證平臺能大幅加快仿真速度,提高驗(yàn)證效率。本論文的主要?jiǎng)?chuàng)新點(diǎn)包括:采用直接編程接口(Direct Programming Interface,DPI)能在C語言域和SV語言域中轉(zhuǎn)換的特點(diǎn),實(shí)現(xiàn)對CPU虛擬模型—cRunner的設(shè)計(jì)。它能把在實(shí)體CPU中的C程序直接轉(zhuǎn)移到仿真器中,實(shí)現(xiàn)C程序的高效快速執(zhí)行,使得BOOT時(shí)間減少了87.7%。使用UVM驗(yàn)證方法學(xué),完成一個(gè)可擴(kuò)展OCP總線功能模型的設(shè)計(jì)。在使用UVM過程中,采用了事務(wù)級建模、動(dòng)態(tài)配置和內(nèi)建工廠等機(jī)制。同時(shí)設(shè)計(jì)了一個(gè)OCP協(xié)議可配置的模塊,擴(kuò)大了該模型的應(yīng)用范圍。這些特性使得該模型作為驗(yàn)證知識產(chǎn)權(quán)(Intellectual Property,IP)兼具有良好的可復(fù)用性和擴(kuò)展性。
[Abstract]:In the last decade, mobile communication baseband chips have attracted wide attention due to the strong growth of wireless communication equipment market. With the increase of design scale and complexity of on-chip system on-chip-SoC, verification becomes more and more important in digital circuits. Based on the research and development of communication baseband SoC chip, the design and optimization of platform in system-level verification are studied in this paper, and the complete optimization solution and test case analysis are given. Firstly, by introducing the basic function and structure of the system level verification platform, the working principle of the SystemVerilog verification platform and the relationship between its components are analyzed in detail. On this basis, the requirements of the existing verification platform are analyzed and the optimization design objectives are put forward. Then, according to the optimization goal, the concrete optimization design method is put forward, that is, the abstract virtualization of some hardware entities is divided into two parts: one is the virtualization of CPU(Central Processing Unit, the other is the abstraction of the bus function model. The virtual model of these two parts is used to replace the entity and simplify the design. For the virtualization of CPU, a model cRunner can be established by simulating the behavior of CPU on the verification platform. It can convert C programs of test cases into SV programs and execute directly on the simulator. The bus model of communication between cRunner and other modules can be designed by open core protocol (Open Core Protocol) and Universal Verification method. It can realize the interface protocol conversion from cRunner to NoC. Thus the register / memory is accessed. The optimized verification platform is called Unified Test bench. The hardware / software co-simulation strategy is adopted in UTB to accelerate the simulation process and verify the simulation under the no core system. The desired optimization design goal is achieved. Finally, the test cases are simulated on the original verification platform and the optimized verification platform. The simulation includes system level simulation and gate level simulation. The actual physical simulation time is reduced by 83.9. It is proved that the optimized verification platform can greatly accelerate the speed of simulation and improve the efficiency of verification. The main innovations of this thesis are as follows: the design of CPU virtual model -cRunner is realized by using direct Programming interface (DPI), which can be converted in C and SV language domains. It can transfer C program in entity CPU directly to the emulator, realize C program execution efficiently and quickly, and reduce the BOOT time by 87.7%. An extensible OCP bus function model is designed using UVM verification methodology. In the process of using UVM, the mechanism of transaction level modeling, dynamic configuration and built-in factory are adopted. At the same time, a configurable module of OCP protocol is designed, which expands the application range of the model. These characteristics make the model have good reusability and extensibility as well as verify intellectual property IPs.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN47

【共引文獻(xiàn)】

相關(guān)期刊論文 前1條

1 成丹;譚星亮;穆峻;;基于UVM及ZeBu的驗(yàn)證系統(tǒng)[J];中國集成電路;2015年11期

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本文編號：1779155