本文選題：AVS編碼器　切入點(diǎn)：FPGA　出處：《太原理工大學(xué)》2013年碩士論文　論文類(lèi)型：學(xué)位論文

【摘要】：AVS標(biāo)準(zhǔn)是中國(guó)數(shù)字音視頻編解碼技術(shù)標(biāo)準(zhǔn)工作組制定的具有自主知識(shí)產(chǎn)權(quán)的數(shù)字音視頻編碼標(biāo)準(zhǔn)。該標(biāo)準(zhǔn)具有較高的編碼效率,達(dá)到了國(guó)際先進(jìn)水平,是高清數(shù)字電視、網(wǎng)絡(luò)電視、視頻通信等重大音視頻應(yīng)用采用的基礎(chǔ)標(biāo)準(zhǔn),并于2006年正式被批準(zhǔn)為新一代音視頻編碼國(guó)家標(biāo)準(zhǔn)。目前,AVS已經(jīng)被聯(lián)通采用作IPTV標(biāo)準(zhǔn),進(jìn)入產(chǎn)業(yè)化推廣階段。AVS標(biāo)準(zhǔn)采用了一系列先進(jìn)技術(shù),兼顧了處理速度和復(fù)雜度兩方面的限制,但是編碼壓縮處理數(shù)據(jù)量大,運(yùn)算復(fù)雜度仍然很高。FPGA具有較高的性能和靈活性,高速的并行運(yùn)算速度和豐富的寄存器資源能夠?qū)崿F(xiàn)復(fù)雜算法的快速處理,是實(shí)現(xiàn)AVS編碼器的最佳選擇之一。AVS編碼處理的數(shù)據(jù)量大,運(yùn)算復(fù)雜度高,同時(shí)為了達(dá)到實(shí)時(shí)編碼的要求,需要很快的運(yùn)算速度。本文提出一種新型架構(gòu)—FPGA上的面向服務(wù)架構(gòu)(SOA),并用于實(shí)現(xiàn)AVS編碼器。根據(jù)以太網(wǎng)傳輸?shù)奶攸c(diǎn),設(shè)計(jì)了片內(nèi)只寫(xiě)總線(BoW)以及基于BoW上的消息訪問(wèn)機(jī)制,并基于此提出實(shí)現(xiàn)BoW的網(wǎng)絡(luò)拓?fù)浣Y(jié)構(gòu)。只寫(xiě)總線BoW的網(wǎng)絡(luò)拓?fù)浣Y(jié)構(gòu)簡(jiǎn)單,它由一個(gè)主處理器節(jié)點(diǎn)(定序器)和若干從處理器節(jié)點(diǎn)(原子構(gòu)件)構(gòu)成,節(jié)點(diǎn)通過(guò)統(tǒng)一節(jié)點(diǎn)接口(UNI)掛接到總線上,降低了原子構(gòu)件引腳互連的復(fù)雜性。提出并設(shè)計(jì)實(shí)現(xiàn)了一種定序器引擎控制流程的執(zhí)行順序,節(jié)點(diǎn)之間的互連采用基于BoW總線的消息傳遞機(jī)制,通信協(xié)議簡(jiǎn)單。以此為基礎(chǔ),本文在FPGA上實(shí)現(xiàn)了AVS編碼器關(guān)鍵算法,包括幀內(nèi)預(yù)測(cè)、殘差/重構(gòu)、DCT/IDCT變換、量化/反量化和熵編碼。利用FPGA開(kāi)發(fā)工具,對(duì)各算法模塊進(jìn)行仿真驗(yàn)證,保證了算法功能的正確性。根據(jù)編碼算法的特點(diǎn),將AVS編碼器的關(guān)鍵算法分為四個(gè)功能模塊,各功能模塊封裝成基于消息訪問(wèn)的原子構(gòu)件,包括圖像采集原子構(gòu)件、預(yù)測(cè)變換原子構(gòu)件、編碼原子構(gòu)件和碼流拼接原子構(gòu)件。為了提高數(shù)據(jù)處理的速度,各功能模塊采用高度并行算法和流水線設(shè)計(jì)方法進(jìn)行優(yōu)化。為了進(jìn)一步提高編碼速度,本文采用總線上重復(fù)部署多個(gè)原子構(gòu)件、多個(gè)流程并行執(zhí)行的方式,從而實(shí)現(xiàn)高分辨率圖像的實(shí)時(shí)編碼。通過(guò)ISE綜合與ModelSim仿真,最高時(shí)鐘頻率可達(dá)130MHz。采用100MHz的系統(tǒng)時(shí)鐘,在Virtex-5平臺(tái)上可實(shí)現(xiàn)D1分辨率Ⅰ幀圖像的實(shí)時(shí)編碼。將實(shí)時(shí)編碼的碼流通過(guò)以太網(wǎng)傳輸系統(tǒng)發(fā)送給客戶(hù)端,經(jīng)解碼器解碼和播放器顯示,驗(yàn)證了AVS編碼器的實(shí)時(shí)編碼能力。
[Abstract]:The AVS standard is China digital audio and video coding standard working group to develop with independent intellectual property rights of digital audio and video encoding standard. This standard has higher encoding efficiency, reached the international advanced level, high-definition digital TV, Internet TV, video communication using basic standard and other major audio and video applications, and in 2006 was officially approved for a new generation of audio and video encoding standards. At present, AVS has been adopted as the standard IPTV Unicom, entered the stage of industrialization of.AVS standard adopts a series of advanced technology, the processing speed and the complexity of the two aspects, but the large number of data compression encoding, the computational complexity is still high.FPGA has high performance and flexibility, fast processing speed to realize complex algorithm parallel computing speed and rich resources to register, which is the best choice for the realization of AVS encoder Choose one of the.AVS encoding processing of large amount of data, high computational complexity, at the same time in order to achieve real-time encoding requirements, need fast computation speed. This paper presents a new architecture of FPGA Service Oriented Architecture (SOA), and for the realization of AVS encoder. According to the characteristics of Ethernet transmission design, write only the on-chip bus (BoW) and BoW based message access mechanism, and put forward the implementation of BoW network topology based on the network topology. Just write simple BoW bus, which consists of a main processor node (sequencer) and a plurality of processor nodes (from atomic components), through a unified interface node node (UNI) attached to the bus, reducing the complexity of atomic components pin interconnection. We designed and implemented a sequencer engine control the execution order of the interconnections between nodes using the transmission mechanism of BoW bus based message pass A simple letter agreement. On this basis, the paper implements the key algorithm of AVS encoder based on FPGA, including intra prediction, residual / reconstruction, DCT/IDCT transform, quantization and inverse quantization and entropy encoding. The use of FPGA development tools, the simulation of the algorithm module, to ensure the correctness of the algorithm. According to the characteristics of the encoding algorithm the key algorithm of AVS encoder is divided into four functional modules, each module is encapsulated into atomic components based on message access, including image acquisition atomic components, prediction transform atomic components, encoding atomic components and bitstream splicing atomic components. In order to improve the speed of data processing, each function module adopts a highly parallel algorithm and pipelining design the method was optimized. In order to further improve the encoding speed, this paper adopts the bus to repeat the deployment of multiple atomic components, multi process parallel execution mode, in order to achieve high resolution Real time image encoding rate. Through ISE and ModelSim simulation, the maximum clock frequency is up to 130MHz. using the 100MHz system clock, on the Virtex-5 platform can realize real-time encoding of D1 resolution frames. The real-time encoding bit stream transmitted through Ethernet transmission system to the client, the decoder and player to display, verify the real-time encoding the ability of AVS encoder.

【學(xué)位授予單位】：太原理工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類(lèi)號(hào)】：TN919.81

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本文編號(hào)：1599313