發(fā)布時間：2018-03-10 01:17

  本文選題：數(shù)字雷達專用芯片　切入點：可編程門陣列　出處：《西安電子科技大學》2014年碩士論文　論文類型：學位論文

【摘要】：數(shù)字雷達系統(tǒng)由于其高精度幅相正交特性、抗干擾性、穩(wěn)定性等優(yōu)勢已經成為新一代雷達體系的主要發(fā)展方向，被更多的應用到全天候遠距離實現(xiàn)對目標的探測和定位，在軍事民用領域如民航交通管制、陸�？毡O(jiān)視、精確制導、導航、汽車防撞與測距以及氣象預報等眾多國民經濟重要部門。同時在微電子技術日新月異的發(fā)展中，F(xiàn)PGA和DSP在信號處理能力上不斷提升，ASIC即專用集成電路能夠實現(xiàn)比DSP和FPGA處理速度更快，功耗更低及更高的可靠性，并擁有自主知識產權的芯片大規(guī)�；a后在價格上具有很大的優(yōu)勢。因此利用最新的片上芯片系統(tǒng)（System on Chip）技術來設計新一代體制的數(shù)字雷達系統(tǒng)成為目前研究的當務之急。 本論文的工作來源于部委研究項目，重點研究數(shù)字雷達接收機信號處理的IP核設計,并且就數(shù)據(jù)通路的性能優(yōu)化、面積優(yōu)化、驗證平臺等方面展開了研究和設計實現(xiàn)工作。主要討論了流水式數(shù)字信號處理器和時分復用方式的電路實現(xiàn)架構。并在時分復用方式下對性能優(yōu)化與電路優(yōu)化兩個方面進行討論并設計了數(shù)據(jù)通路。并且最終實現(xiàn)了兩個優(yōu)化條件下的數(shù)據(jù)通路框架設計。 本論文工作在雷達接收通道SoC原型系統(tǒng)設計實驗和板級驗證平臺的實現(xiàn)基礎上，對主要雷達信號進行了驗證測試。測試數(shù)據(jù)結果表明功能滿足要求。在SMIC0.13um工藝下，性能優(yōu)化中最高中頻信號吞吐率為2GSPS，，面積優(yōu)化中數(shù)據(jù)通路面積約0.05mm2。實驗結果說明本系統(tǒng)設計和驗證平臺達到了項目設計指標要求，為進一步SoC芯片實驗奠定了良好的基礎。
[Abstract]:The digital radar system has become the main development direction of the new generation radar system because of its high precision amplitude-phase orthogonality, anti-jamming, stability and so on. In military and civilian areas such as civil aviation traffic control, land, sea and air surveillance, precision guidance, navigation, At the same time, with the rapid development of microelectronics technology, FPGA and DSP continuously improve their signal processing capability, that is, ASIC can achieve better performance than DSP. And FPGA process faster, Lower power consumption and higher reliability, And the chip with independent intellectual property has a great advantage in price after large-scale production, so it is urgent to design a new generation of digital radar system by using the latest chip system system on chip Chiptechnology. The work of this paper comes from the research project of the ministry, focusing on the IP core design of digital radar receiver signal processing, and the performance optimization and area optimization of the data path. This paper mainly discusses the circuit implementation architecture of income type digital signal processor and time division multiplexing mode, and optimizes the performance and circuit under the time division multiplexing mode. Finally, the data path framework under two optimized conditions is designed. Based on the design experiment of radar receiving channel SoC prototype system and the realization of board level verification platform, the main radar signals are verified and tested. The test results show that the function meets the requirements. Under the SMIC0.13um technology, the main radar signals are verified and tested. In the performance optimization, the maximum if signal throughput is 2GSPS, and the data path area is about 0.05mm2.The experimental results show that the system design and verification platform meets the project design requirements, and lays a good foundation for further SoC chip experiments.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN957.5

【參考文獻】

相關期刊論文 前5條

1 龍騰,戴險峰,孫亞民,李眈;基于專用芯片的高速實時 FFT 系統(tǒng)實現(xiàn)研究[J];北京理工大學學報;1997年06期

2 蔣小燕;孫曉薇;胡恒陽;錢顯毅;;基于FPGA的FIR數(shù)字濾波器的設計與實現(xiàn)[J];常州工學院學報;2011年02期

3 張長耀,宋秀芬;ASIC電路在雷達信號處理中的應用[J];微電子學;1999年03期

4 李雷;齊精兵;;基于FPGA的雷達信號處理方法探究[J];中國新通信;2013年15期

5 趙艷;;基于DSP的雷達多目標模擬器的設計和實現(xiàn)[J];戰(zhàn)術導彈技術;2007年04期

本文編號：1591125