本文關(guān)鍵詞： 主動硬件防偽控制 物理不可克隆函數(shù) 有限狀態(tài)機 硬件水印驗證 FPGA　出處：《湖南大學(xué)》2013年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著知識產(chǎn)權(quán)核可重用技術(shù)在半導(dǎo)體領(lǐng)域中的普遍應(yīng)用，知識產(chǎn)權(quán)核(IP)的盜版、復(fù)制和非法過量生產(chǎn)等問題日益嚴(yán)重，給IP核設(shè)計者造成了巨大的利益損失，硬件知識產(chǎn)權(quán)核(IP)的保護技術(shù)的研究正變得愈來愈重要。硬件防偽控制是指一系列方案，它使得IP設(shè)計者能對IC的后生產(chǎn)階段進行有效的控制，從而達到保護IP核和阻止生產(chǎn)廠商非法過量生產(chǎn)目的。硬件水印是一種新興的IP核保護技術(shù)，它通過在IP核中嵌入設(shè)計者的標(biāo)識來對IP核的所有權(quán)進行有效標(biāo)識和認(rèn)證。硬件防偽控制和硬件水印技術(shù)的研究對半導(dǎo)體產(chǎn)業(yè)的知識產(chǎn)權(quán)核保護具有重要意義。本文著力于研究高安全、低開銷的主動IC防偽控制方案和高效比特級硬件水印提取驗證方案，主要工作有： (1)針對現(xiàn)有主動硬件防偽控制方案存在的安全性和開銷等問題，提出了一種新的基于FSM的主動硬件防偽控制層次型結(jié)構(gòu)。該結(jié)構(gòu)作為額外加入原始FSM的控制鎖定部分，通過與物理不可克隆函數(shù)進行綁定，，構(gòu)成一個FSM鎖對生產(chǎn)廠商生產(chǎn)出來的每塊IC芯片中的IP核進行唯一鎖定。每個生產(chǎn)的IC芯片起電時跳到一個固定的起始鎖定狀態(tài)，IC生產(chǎn)廠商只有通過將該IC的唯一PUF標(biāo)識傳回給IP核設(shè)計者，才能獲得相應(yīng)唯一的解鎖密鑰和剩下位數(shù)的跳轉(zhuǎn)輸入值，以激活I(lǐng)C進行解鎖。提出的層次型防偽控制方案首先利用PUF的響應(yīng)來決定解鎖路徑，隨后利用FSM跳轉(zhuǎn)輸入位數(shù)以提高其抵抗窮舉型攻擊的魯棒性。與現(xiàn)有相關(guān)硬件防偽結(jié)構(gòu)相比，提出的結(jié)構(gòu)有更好的安全性以抵抗窮舉攻擊。本文在Berkeley SIS平臺上對兩種方案在MCNC基準(zhǔn)電路上的面積、時延和功耗開銷進行了實驗，實驗結(jié)果表明方案的開銷在可以接受的范圍。 (2)很多現(xiàn)存的水印技術(shù)需要依賴FPGA工具手動從比特文件中提取水印或者需要在比特文件中進行窮舉搜索來尋找水印，造成了水印驗證的低效性。本文提出了一種使用FPGA中LUT單元內(nèi)容提取的方法來對比特級水印進行有效地提取驗證，從而達到高效驗證IP所有權(quán)的目的。該方法通過對FPGA中查找表內(nèi)容在比特文件中的存儲位置的分析來從比特文件中提取水印，提取出的各水印部分再進行重新組合后解密為簽名，以此使IP核的所有權(quán)得到迅速和有效地驗證。
[Abstract]:With the widespread application of IPR in semiconductor field, the problems of IP piracy, reproduction and illegal overproduction are becoming more and more serious, which has caused huge loss of benefits to IP core designers. Hardware anti-counterfeiting control refers to a series of schemes, which enable IP designers to effectively control the post-production stage of IC. In order to protect the IP core and prevent the manufacturers from illegally overproducing, the hardware watermark is a new IP core protection technology. It can effectively identify and authenticate the ownership of IP core by embedding the designer's logo in the IP core. The research of hardware anti-counterfeiting control and hardware watermarking technology is of great significance to the intellectual property core protection of semiconductor industry. This paper focuses on the study of high security, The low cost active IC anti-counterfeiting control scheme and the high efficiency hardware watermark extraction and verification scheme, the main work is as follows:. 1) aiming at the security and overhead problems existing in the existing active hardware anti-counterfeiting control schemes, a new active hardware anti-counterfeiting control hierarchy based on FSM is proposed, which is used as a locking part of the active hardware anti-counterfeiting control scheme with the addition of the original FSM. By binding to physically noncloned functions, A FSM lock is formed to uniquely lock the IP core in each IC chip produced by the manufacturer. Each IC chip is switched on to a fixed initial locking state. An PUF ID is returned to the IP core designer, In order to obtain the corresponding unique unlock key and the jump input value of the remaining digits to activate the IC to unlock, the hierarchical anti-counterfeiting control scheme first uses the response of PUF to determine the unlock path. Then the FSM jump input bits are used to improve its robustness against exhaustive attacks. Compared with the existing hardware anti-counterfeiting architecture, The proposed structure has better security against exhaustive attacks. In this paper, the area, delay and power overhead of the two schemes in the MCNC reference circuit are tested on the Berkeley SIS platform. The experimental results show that the cost of the scheme is within an acceptable range. Many existing watermarking technologies need to rely on FPGA tools to manually extract the watermark from the bit file or search through the bit file to find the watermark. In this paper, a method of extracting the content of LUT unit in FPGA is proposed to compare the high level watermark and verify it effectively. In order to verify IP ownership efficiently, this method extracts watermark from bit files by analyzing the storage location of table contents in bit files in FPGA. The extracted watermarks are recombined and decrypted as signatures, so that the ownership of IP cores can be verified quickly and effectively.
【學(xué)位授予單位】：湖南大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP309

【參考文獻】

相關(guān)期刊論文 前6條

1 李東曉;鄭偉;張明;;IP芯核水印技術(shù)研究進展[J];電路與系統(tǒng)學(xué)報;2007年04期

2 聶廷遠;劉海濤;周立儉;李言勝;;FPGA IP核數(shù)字水印保護與檢測技術(shù)[J];半導(dǎo)體技術(shù);2012年08期

3 張學(xué)龍;汪鵬君;張躍軍;;基于電流鏡的電流型PUF電路設(shè)計[J];電路與系統(tǒng)學(xué)報;2013年01期

4 項群良;張培勇;歐陽冬生;馮忱暉;;多頻率段物理不可克隆函數(shù)[J];電子與信息學(xué)報;2012年08期

5 聶廷遠;劉海濤;周立儉;李言勝;;利用LUT替換的FPGA保護數(shù)字水印技術(shù)[J];微電子學(xué)與計算機;2013年01期

6 吳志安;段成華;;采用全局互連線隨機模型的硅物理不可克隆函數(shù)的設(shè)計[J];微電子學(xué)與計算機;2012年12期

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